DAC Design with PCM1795 and STM32

I found the previous connector-only blocks. I’m removing those and replacing them with actual ICs and analog-stage components now.
Rebuilt the project as a real IC-level schematic instead of connector blocks: PCM1795, 3× OPA1612, LT3042 3.3 V/5 V rails, I/V feedback networks, differential output stage, RCA outputs, and power/input headers are now present and wired. ERC checks are currently clean for the checks run, and the project spec was updated.
Open items:
  • The PCB layout is not done yet; per workflow, this is the schematic checkpoint before layout.
  • The PCM1795 library symbol/footprint must be visually checked against the TI datasheet pinout before fabrication.
  • STM32F407 exact I2S/SPI GPIO mapping is still your next firmware/pinout decision.
Suggested next steps:
  1. Review the schematic view and confirm it now looks like the detailed circuit you expected.
  2. I can next create the physical PCB placement with DAC + OPA stages tightly clustered.
  3. After placement approval, I can route the board with low-noise analog layout rules.
Proceed to placement
Verify PCM1795 symbol
Explain schematic
Layout best practices
Run deeper review
U1 IOUTL- - U2 -IN B
DAC_RST_N
U2 OUT A - R1 P2
J2 3 - U2 V+
R9 P2 - U4 +IN A
U3 OUT A - R3 P2
U2 OUT A - R1 P2
U1 AGND3R - C9 P2
U1 IOUTR+ - U3 -IN A
U1 IREF - C13 P1
J2 4 - U2 V-
U1 AGND3R - C9 P2
U3 +IN A - R7 P1
U1 AGND3R - C9 P2
J2 4 - U2 V-
U1 VCC2R - C10 P1
J2 4 - U2 V-
U5 OUTS - U1 VDD
U1 AGND3R - C9 P2
J2 3 - U2 V+
R9 P2 - U4 +IN A
J2 4 - U2 V-
R15 P2 - U4 -IN B
C14 P1 - C15 P1
J1 Pin_2 - R20 P1
C14 P1 - C15 P1
J2 1 - U5 IN_1
R19 P2 - U1 LRCK
U1 IOUTL+ - U2 -IN A
U3 +IN B - R8 P1
U3 +IN A - R7 P1
U1 VCC2R - C10 P1
J2 3 - U2 V+
U1 IOUTL+ - U2 -IN A
R23 P1 - U5 SET
J2 4 - U2 V-
J2 4 - U2 V-
U2 OUT A - R1 P2
U3 OUT A - R3 P2
J1 Pin_5 - U1 ~MS
J2 3 - U2 V+
R21 P2 - U1 BCK
U6 EN/UV - C32 P1
U3 OUT B - R4 P2
R13 P2 - U4 +IN B
R9 P2 - U4 +IN A
U1 AGND3R - C9 P2
U5 OUTS - U1 VDD
U1 AGND3R - C9 P2
U5 OUTS - U1 VDD
U5 OUTS - U1 VDD
J1 Pin_4 - R22 P1
U2 OUT B - R2 P2
R15 P2 - U4 -IN B
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
R20 P2 - U1 DATA
R13 P2 - U4 +IN B
R15 P2 - U4 -IN B
J2 3 - U2 V+
U1 AGND3R - C9 P2
C14 P1 - C15 P1
U1 AGND3R - C9 P2
J1 Pin_5 - U1 ~MS
C14 P1 - C15 P1
R24 P1 - U6 SET
J1 Pin_1 - R19 P1
R11 P2 - U4 -IN A
U1 IOUTR- - U3 -IN B
J1 Pin_7 - U1 MC
U1 VCC2R - C10 P1
U1 IOUTR+ - U3 -IN A
U5 OUTS - U1 VDD
U1 AGND3R - C9 P2
U2 OUT B - R2 P2
U4 OUT A - R12 P2
U2 +IN A - R5 P1
U1 AGND3R - C9 P2
J1 Pin_3 - R21 P1
J1 Pin_4 - R22 P1
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U4 OUT A - R12 P2
U4 OUT B - R16 P2
C14 P1 - C15 P1
J2 3 - U2 V+
U3 OUT B - R4 P2
DAC_RST_N
U5 EN/UV - C30 P1
J1 Pin_1 - R19 P1
R21 P2 - U1 BCK
R17 P2 - J3 1
U1 AGND3R - C9 P2
U6 EN/UV - C32 P1
U1 IREF - C13 P1
J2 2 - U6 IN_1
U1 VCC2R - C10 P1
C14 P1 - C15 P1
U1 VCOML - C11 P1
R19 P2 - U1 LRCK
R23 P1 - U5 SET
U1 AGND3R - C9 P2
U1 IOUTR- - U3 -IN B
R20 P2 - U1 DATA
U5 OUTS - U1 VDD
U2 +IN B - R6 P1
R17 P2 - J3 1
R24 P1 - U6 SET
U1 AGND3R - C9 P2
R23 P1 - U5 SET
U1 IOUTR+ - U3 -IN A
U1 VCOMR - C12 P1
J1 Pin_3 - R21 P1
U1 IOUTL- - U2 -IN B
R11 P2 - U4 -IN A
U1 IOUTR- - U3 -IN B
J2 4 - U2 V-
U3 OUT A - R3 P2
U3 OUT B - R4 P2
R11 P2 - U4 -IN A
U2 OUT B - R2 P2
U5 EN/UV - C30 P1
U1 IOUTL+ - U2 -IN A
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U4 OUT B - R16 P2
U4 OUT B - R16 P2
R22 P2 - U1 SCL
U2 OUT B - R2 P2
R18 P2 - J4 1
R24 P1 - U6 SET
U2 +IN A - R5 P1
U1 AGND3R - C9 P2
R22 P2 - U1 SCL
R17 P2 - J3 1
U4 OUT B - R16 P2
U1 AGND3R - C9 P2
U3 OUT A - R3 P2
J1 Pin_2 - R20 P1
U1 VCOML - C11 P1
R11 P2 - U4 -IN A
U2 +IN B - R6 P1
U2 OUT A - R1 P2
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U1 VCOMR - C12 P1
U5 OUTS - U1 VDD
U1 AGND3R - C9 P2
J2 4 - U2 V-
U1 AGND3R - C9 P2
U4 OUT A - R12 P2
U1 IOUTL- - U2 -IN B
J2 2 - U6 IN_1
J2 1 - U5 IN_1
U1 IOUTL- - U2 -IN B
J2 3 - U2 V+
U1 IOUTR- - U3 -IN B
U3 +IN B - R8 P1
U1 AGND3R - C9 P2
U1 VCC2R - C10 P1
R15 P2 - U4 -IN B
U4 OUT A - R12 P2
J1 Pin_7 - U1 MC
U1 AGND3R - C9 P2
J1 Pin_6 - U1 MDI
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U3 OUT B - R4 P2
U1 AGND3R - C9 P2
R18 P2 - J4 1
U1 IOUTR+ - U3 -IN A
J2 3 - U2 V+
U1 AGND3R - C9 P2
J1 Pin_6 - U1 MDI
U1 AGND3R - C9 P2
R18 P2 - J4 1
U1 IOUTL+ - U2 -IN A
R13 P2 - U4 +IN B
C18
Capacitance
100nF
C19
Capacitance
10uF
C7
Capacitance
2.2nF
C12
Capacitance
100nF
C23
Capacitance
10uF
C14
Capacitance
100nF
C26
Capacitance
10uF
C25
Capacitance
10uF
C1
Capacitance
47pF
C3
Capacitance
47pF
C21
Capacitance
10uF
C16
Capacitance
100nF
C6
Capacitance
220pF
C24
Capacitance
10uF
C22
Capacitance
10uF
C10
Capacitance
100nF
C13
Capacitance
100nF
C20
Capacitance
10uF
C32
Capacitance
10uF
C33
Capacitance
10uF
C30
Capacitance
10uF
C9
Capacitance
100nF
C15
Capacitance
100nF
C27
Capacitance
47uF
C8
Capacitance
2.2nF
C5
Capacitance
220pF
C29
Capacitance
47uF
C35
Capacitance
4.7uF
C11
Capacitance
100nF
C4
Capacitance
47pF
C17
Capacitance
100nF
C2
Capacitance
47pF
C31
Capacitance
10uF
C28
Capacitance
47uF
C34
Capacitance
4.7uF
R23 P2 - C34 P2
R7
Resistance
680Ω
R23
Resistance
33.2kΩ
U5 GND_1 - U5 GND_2
U5 GND_1 - U5 GND_2
GND
U5 GND_1 - U5 GND_2
R5
Resistance
680Ω
R20
Resistance
27Ω
GND
R21
Resistance
27Ω
GND
R18
Resistance
100Ω
J5 Pin_5 - R26 P1
R8
Resistance
680Ω
R26
Resistance
R23 P2 - C34 P2
R25
Resistance
10kΩ
R9
Resistance
10kΩ
R23 P2 - C34 P2
U5 GND_1 - U5 GND_2
U5 GND_1 - U5 GND_2
R24
Resistance
49.9kΩ
R19
Resistance
27Ω
R22
Resistance
27Ω
R3
Resistance
680Ω
R4
Resistance
680Ω
J5 Pin_5 - R26 P1
R17
Resistance
100Ω
R6
Resistance
680Ω
R2
Resistance
680Ω
R11
Resistance
10kΩ
U5 GND_1 - U5 GND_2
U5 GND_1 - U5 GND_2
R12
Resistance
10kΩ
R14
Resistance
10kΩ
R15
Resistance
10kΩ
R23 P2 - C34 P2
GND
R16
Resistance
10kΩ
U5 GND_1 - U5 GND_2
R13
Resistance
10kΩ
R10
Resistance
10kΩ
R1
Resistance
680Ω
U3
U4
J5
U2
U5
U6
J1
U1
J4
J3

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Firmware Starter — STM32F407 PCM1795 DAC Source
Platform & Toolchain
  • MCU board: External STM32F407 board
  • Framework: STM32 HAL / STM32CubeIDE
  • Purpose: Generate I2S audio clocks/data and configure PCM1795 over SPI/control pins.
Pin Mapping
Exact STM32 GPIO pins depend on the specific STM32F407 board header wiring. The schematic currently names the board-level connector nets:

Table


FunctionSchematic NetSTM32 PeripheralDirectionNotes
Bit clockI2S_BCKSPI/I2Sx_CKMCU → DACSelect an STM32 I2S-capable pin.
Word selectI2S_LRCKSPI/I2Sx_WSMCU → DACAlso called LRCK/WS.
Audio dataI2S_DATASPI/I2Sx_SDMCU → DACPCM audio data stream.
Master clockI2S_MCLKSPI/I2Sx_MCKMCU → DACUse if the PCM1795 board requires external MCLK.
Control clockSPI_SCKSPIx_SCKMCU → DACPCM1795 control port.
Control data inSPI_MOSISPIx_MOSIMCU → DACRegister writes.
Control data outSPI_MISOSPIx_MISODAC → MCUOptional, if DAC board exposes readback.
Chip selectDAC_CSGPIO outputMCU → DACActive level to confirm from board.
ResetDAC_RSTGPIO outputMCU → DACActive level to confirm from board.
MuteDAC_MUTEGPIO outputMCU → DACActive level to confirm from board.
Example STM32 HAL Source Skeleton

C


#include "main.h"
#include <string.h>

I2S_HandleTypeDef hi2s3;
SPI_HandleTypeDef hspi1;

#define DAC_CS_GPIO_Port     GPIOA
#define DAC_CS_Pin           GPIO_PIN_4
#define DAC_RST_GPIO_Port    GPIOA
#define DAC_RST_Pin          GPIO_PIN_0
#define DAC_MUTE_GPIO_Port   GPIOA
#define DAC_MUTE_Pin         GPIO_PIN_1

static void dac_cs_low(void)  { HAL_GPIO_WritePin(DAC_CS_GPIO_Port, DAC_CS_Pin, GPIO_PIN_RESET); }
static void dac_cs_high(void) { HAL_GPIO_WritePin(DAC_CS_GPIO_Port, DAC_CS_Pin, GPIO_PIN_SET); }

static HAL_StatusTypeDef pcm1795_write_reg(uint8_t reg, uint8_t value) {
    uint8_t frame[2];
    frame[0] = reg;
    frame[1] = value;
    dac_cs_low();
    HAL_StatusTypeDef st = HAL_SPI_Transmit(&hspi1, frame, sizeof(frame), HAL_MAX_DELAY);
    dac_cs_high();
    return st;
}

static void pcm1795_reset_sequence(void) {
    HAL_GPIO_WritePin(DAC_RST_GPIO_Port, DAC_RST_Pin, GPIO_PIN_RESET);
    HAL_Delay(10);
    HAL_GPIO_WritePin(DAC_RST_GPIO_Port, DAC_RST_Pin, GPIO_PIN_SET);
    HAL_Delay(10);
}

static void pcm1795_init(void) {
    dac_cs_high();
    HAL_GPIO_WritePin(DAC_MUTE_GPIO_Port, DAC_MUTE_Pin, GPIO_PIN_SET);
    pcm1795_reset_sequence();

    // TODO: Replace register addresses/values with the exact PCM1795 board mode.
    // Configure audio format, oversampling, de-emphasis, and mute control per PCM1795 datasheet.
    // pcm1795_write_reg(REGISTER_ADDR, REGISTER_VALUE);

    HAL_GPIO_WritePin(DAC_MUTE_GPIO_Port, DAC_MUTE_Pin, GPIO_PIN_RESET);
}

int main(void) {
    HAL_Init();
    SystemClock_Config();
    MX_GPIO_Init();
    MX_SPI1_Init();
    MX_I2S3_Init();

    pcm1795_init();

    // Example 16-bit stereo silence buffer. Replace with real PCM stream.
    uint16_t silence[128] = {0};

    while (1) {
        HAL_I2S_Transmit(&hi2s3, silence, 128, HAL_MAX_DELAY);
    }
}
Build & Flash Instructions
  1. Create an STM32CubeIDE project for the exact STM32F407 board.
  2. Enable one SPI peripheral in I2S master transmit mode for BCK/LRCK/DATA/MCLK.
  3. Enable one SPI peripheral or GPIO bit-banged interface for PCM1795 control.
  4. Map the GPIO labels above to the actual header pins used on the STM32F407 board.
  5. Build and flash with ST-LINK or the board's onboard programmer.
TODO Before Hardware Bring-Up
  • Confirm exact STM32F407 board model and available I2S pins.
  • Confirm PCM1795 board pinout and whether MCLK is required.
  • Confirm PCM1795 register settings for I2S word length, sample rate, and analog output mode.
  • Platform & Toolchain

  • Pin Mapping

  • Example STM32 HAL Source Skeleton

  • Build & Flash Instructions

  • TODO Before Hardware Bring-Up

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STM32F407 PCM1795 DAC Interconnect

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$25.95–$40.88

Digi-Key

$29.05

LCSC

$51.13

Mouser

$53.18

TME

$24.18

Verical

$20.45–$1,046.42

Controls