DAC Design with PCM1795 and STM32

I found the previous connector-only blocks. I’m removing those and replacing them with actual ICs and analog-stage components now.
Rebuilt the project as a real IC-level schematic instead of connector blocks: PCM1795, 3× OPA1612, LT3042 3.3 V/5 V rails, I/V feedback networks, differential output stage, RCA outputs, and power/input headers are now present and wired. ERC checks are currently clean for the checks run, and the project spec was updated.
Open items:
  • The PCB layout is not done yet; per workflow, this is the schematic checkpoint before layout.
  • The PCM1795 library symbol/footprint must be visually checked against the TI datasheet pinout before fabrication.
  • STM32F407 exact I2S/SPI GPIO mapping is still your next firmware/pinout decision.
Suggested next steps:
  1. Review the schematic view and confirm it now looks like the detailed circuit you expected.
  2. I can next create the physical PCB placement with DAC + OPA stages tightly clustered.
  3. After placement approval, I can route the board with low-noise analog layout rules.
Proceed to placement
Verify PCM1795 symbol
Explain schematic
Layout best practices
Run deeper review
U1 IOUTL- - U2 -IN B
DAC_RST_N
U2 OUT A - R1 P2
J2 3 - U2 V+
R9 P2 - U4 +IN A
U3 OUT A - R3 P2
U2 OUT A - R1 P2
U1 AGND3R - C9 P2
U1 IOUTR+ - U3 -IN A
U1 IREF - C13 P1
J2 4 - U2 V-
U1 AGND3R - C9 P2
U3 +IN A - R7 P1
U1 AGND3R - C9 P2
J2 4 - U2 V-
U1 VCC2R - C10 P1
J2 4 - U2 V-
U5 OUTS - U1 VDD
U1 AGND3R - C9 P2
J2 3 - U2 V+
R9 P2 - U4 +IN A
J2 4 - U2 V-
R15 P2 - U4 -IN B
C14 P1 - C15 P1
J1 Pin_2 - R20 P1
C14 P1 - C15 P1
J2 1 - U5 IN_1
R19 P2 - U1 LRCK
U1 IOUTL+ - U2 -IN A
U3 +IN B - R8 P1
U3 +IN A - R7 P1
U1 VCC2R - C10 P1
J2 3 - U2 V+
U1 IOUTL+ - U2 -IN A
R23 P1 - U5 SET
J2 4 - U2 V-
J2 4 - U2 V-
U2 OUT A - R1 P2
U3 OUT A - R3 P2
J1 Pin_5 - U1 ~MS
J2 3 - U2 V+
R21 P2 - U1 BCK
U6 EN/UV - C32 P1
U3 OUT B - R4 P2
R13 P2 - U4 +IN B
R9 P2 - U4 +IN A
U1 AGND3R - C9 P2
U5 OUTS - U1 VDD
U1 AGND3R - C9 P2
U5 OUTS - U1 VDD
U5 OUTS - U1 VDD
J1 Pin_4 - R22 P1
U2 OUT B - R2 P2
R15 P2 - U4 -IN B
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
R20 P2 - U1 DATA
R13 P2 - U4 +IN B
R15 P2 - U4 -IN B
J2 3 - U2 V+
U1 AGND3R - C9 P2
C14 P1 - C15 P1
U1 AGND3R - C9 P2
J1 Pin_5 - U1 ~MS
C14 P1 - C15 P1
R24 P1 - U6 SET
J1 Pin_1 - R19 P1
R11 P2 - U4 -IN A
U1 IOUTR- - U3 -IN B
J1 Pin_7 - U1 MC
U1 VCC2R - C10 P1
U1 IOUTR+ - U3 -IN A
U5 OUTS - U1 VDD
U1 AGND3R - C9 P2
U2 OUT B - R2 P2
U4 OUT A - R12 P2
U2 +IN A - R5 P1
U1 AGND3R - C9 P2
J1 Pin_3 - R21 P1
J1 Pin_4 - R22 P1
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U4 OUT A - R12 P2
U4 OUT B - R16 P2
C14 P1 - C15 P1
J2 3 - U2 V+
U3 OUT B - R4 P2
DAC_RST_N
U5 EN/UV - C30 P1
J1 Pin_1 - R19 P1
R21 P2 - U1 BCK
R17 P2 - J3 1
U1 AGND3R - C9 P2
U6 EN/UV - C32 P1
U1 IREF - C13 P1
J2 2 - U6 IN_1
U1 VCC2R - C10 P1
C14 P1 - C15 P1
U1 VCOML - C11 P1
R19 P2 - U1 LRCK
R23 P1 - U5 SET
U1 AGND3R - C9 P2
U1 IOUTR- - U3 -IN B
R20 P2 - U1 DATA
U5 OUTS - U1 VDD
U2 +IN B - R6 P1
R17 P2 - J3 1
R24 P1 - U6 SET
U1 AGND3R - C9 P2
R23 P1 - U5 SET
U1 IOUTR+ - U3 -IN A
U1 VCOMR - C12 P1
J1 Pin_3 - R21 P1
U1 IOUTL- - U2 -IN B
R11 P2 - U4 -IN A
U1 IOUTR- - U3 -IN B
J2 4 - U2 V-
U3 OUT A - R3 P2
U3 OUT B - R4 P2
R11 P2 - U4 -IN A
U2 OUT B - R2 P2
U5 EN/UV - C30 P1
U1 IOUTL+ - U2 -IN A
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U4 OUT B - R16 P2
U4 OUT B - R16 P2
R22 P2 - U1 SCL
U2 OUT B - R2 P2
R18 P2 - J4 1
R24 P1 - U6 SET
U2 +IN A - R5 P1
U1 AGND3R - C9 P2
R22 P2 - U1 SCL
R17 P2 - J3 1
U4 OUT B - R16 P2
U1 AGND3R - C9 P2
U3 OUT A - R3 P2
J1 Pin_2 - R20 P1
U1 VCOML - C11 P1
R11 P2 - U4 -IN A
U2 +IN B - R6 P1
U2 OUT A - R1 P2
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U1 VCOMR - C12 P1
U5 OUTS - U1 VDD
U1 AGND3R - C9 P2
J2 4 - U2 V-
U1 AGND3R - C9 P2
U4 OUT A - R12 P2
U1 IOUTL- - U2 -IN B
J2 2 - U6 IN_1
J2 1 - U5 IN_1
U1 IOUTL- - U2 -IN B
J2 3 - U2 V+
U1 IOUTR- - U3 -IN B
U3 +IN B - R8 P1
U1 AGND3R - C9 P2
U1 VCC2R - C10 P1
R15 P2 - U4 -IN B
U4 OUT A - R12 P2
J1 Pin_7 - U1 MC
U1 AGND3R - C9 P2
J1 Pin_6 - U1 MDI
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U1 AGND3R - C9 P2
U3 OUT B - R4 P2
U1 AGND3R - C9 P2
R18 P2 - J4 1
U1 IOUTR+ - U3 -IN A
J2 3 - U2 V+
U1 AGND3R - C9 P2
J1 Pin_6 - U1 MDI
U1 AGND3R - C9 P2
R18 P2 - J4 1
U1 IOUTL+ - U2 -IN A
R13 P2 - U4 +IN B
C18
Capacitance
100nF
R23 P2 - C34 P2
C19
Capacitance
10uF
U5 GND_1 - U5 GND_2
C7
Capacitance
2.2nF
U5 GND_1 - U5 GND_2
C12
Capacitance
100nF
GND
U5 GND_1 - U5 GND_2
C23
Capacitance
10uF
C14
Capacitance
100nF
C26
Capacitance
10uF
GND
C25
Capacitance
10uF
GND
C1
Capacitance
47pF
C3
Capacitance
47pF
J5 Pin_5 - R26 P1
C21
Capacitance
10uF
C16
Capacitance
100nF
C6
Capacitance
220pF
R23 P2 - C34 P2
C24
Capacitance
10uF
R23 P2 - C34 P2
U5 GND_1 - U5 GND_2
U5 GND_1 - U5 GND_2
C22
Capacitance
10uF
C10
Capacitance
100nF
C13
Capacitance
100nF
J5 Pin_5 - R26 P1
C20
Capacitance
10uF
C32
Capacitance
10uF
C33
Capacitance
10uF
U5 GND_1 - U5 GND_2
C30
Capacitance
10uF
C9
Capacitance
100nF
C15
Capacitance
100nF
C27
Capacitance
47uF
U5 GND_1 - U5 GND_2
C8
Capacitance
2.2nF
C5
Capacitance
220pF
R23 P2 - C34 P2
C29
Capacitance
47uF
C35
Capacitance
4.7uF
C11
Capacitance
100nF
C4
Capacitance
47pF
C17
Capacitance
100nF
GND
C2
Capacitance
47pF
C31
Capacitance
10uF
U5 GND_1 - U5 GND_2
C28
Capacitance
47uF
C34
Capacitance
4.7uF
R7
Resistance
680Ω
R23
Resistance
33.2kΩ
R5
Resistance
680Ω
R20
Resistance
27Ω
R21
Resistance
27Ω
R18
Resistance
100Ω
R8
Resistance
680Ω
R26
Resistance
R25
Resistance
10kΩ
R9
Resistance
10kΩ
R24
Resistance
49.9kΩ
R19
Resistance
27Ω
R22
Resistance
27Ω
R3
Resistance
680Ω
R4
Resistance
680Ω
R17
Resistance
100Ω
R6
Resistance
680Ω
R2
Resistance
680Ω
R11
Resistance
10kΩ
R12
Resistance
10kΩ
R14
Resistance
10kΩ
R15
Resistance
10kΩ
R16
Resistance
10kΩ
R13
Resistance
10kΩ
R10
Resistance
10kΩ
R1
Resistance
680Ω
U3
U4
J5
U2
U5
U6
J1
U1
J4
J3

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Hi-Fi DAC Prototype Wiring Recommendations
Observations From Uploaded Prototype Photos
  • The PCM1795 appears to be mounted on a TSSOP56 breakout/adapter board placed on perfboard.
  • Three small SOIC-8 op-amp modules are mounted nearby; this matches the uploaded schematic using three OPA1612 dual op-amps.
  • The OPA modules are physically close to the DAC adapter, which is good for short analog current-output / I/V paths.
  • The perfboard has many unused copper pads and no obvious continuous ground plane, so return-path control must be done deliberately with short ground wiring, local star points, or copper bus wiring.
Confirmed From Uploaded Schematic PDF
  • DAC: PCM1795 current-output stereo DAC.
  • Op-amps: 3× OPA1612 dual op-amps.
  • Digital source: STM32F407 I2S3 TX.
  • Rails:
    • LT3042 3.3 V for PCM1795 digital/control rail.
    • LT3042 5 V for PCM1795 analog rail.
    • +12 V / −12 V for OPA1612 analog stages.
  • I/V stage:
    • Four I/V converters: IOUTL+, IOUTL−, IOUTR+, IOUTR−.
    • RF = 680 Ω 0.1% starting value.
    • CF = 47–100 pF C0G/NP0 in parallel with RF.
    • Non-inverting bias: 680 Ω to AGND.
  • Differential/output stage:
    • U3A/U3B unity-gain differential amplifier / LPF / buffer.
    • 10 kΩ 0.1% matched resistor network.
    • 220 pF HF filter capacitors.
    • 100 Ω series output resistor before RCA.
    • Optional 2.2 nF output RF shunt.
Priority Rules
  1. Keep DAC current-output / I/V nodes shortest. PCM1795 output pins into the first OPA1612 stage are the most sensitive and should be nearly point-to-point.
  2. Route every signal with its return. On perfboard, loose single wires create loop area and hum pickup.
  3. Separate digital clocks from OPA input nodes. I2S_BCK, I2S_LRCK, I2S_MCLK, SPI_SCK, and STM32 wiring should stay on the opposite side of the DAC adapter from the OPA input wiring if possible.
  4. Use one controlled ground strategy. Avoid multiple accidental joins through USB, oscilloscope earth, supply earth, and amplifier earth.
  5. Verify OPA stability before listening tests. OPA1612 is fast and can oscillate if feedback wiring is long or output cables are capacitive.

Table


LinkPreferred wiringNotes
STM32F407 → PCM1795 I2S/SPIShort ribbon with ground between/adjacent to clock lines, or twisted signal/ground pairsInstall 22–47 Ω source series resistors near STM32 on BCK, LRCK, DATA, optional MCLK.
PCM1795 → first OPA1612 I/V stageShort direct insulated wires or solder bridges; each output routed with nearby AGND/referenceHighest sensitivity. Avoid running these across unused perfboard rows.
I/V feedback loopsComponents directly at OPA pinsRF 680 Ω and CF 47–100 pF must be physically tight around the inverting input/output.
OPA interstage wiringShort twisted pair or direct local routingUse matched 10 kΩ 0.1% network for U3 diff stage.
Final line outShielded audio cable or twisted pair with ground100 Ω series output; optional 2.2 nF shunt only if RF/noise issue appears.
Linear supply railsTwisted supply/return pairs to each functional blockDo not daisy-chain high-current returns through the DAC/OPA input ground.
Grounding Strategy
  • Use a defined local analog ground node close to the DAC/OPA cluster.
  • Bring DAC AGND, OPA signal ground, and analog supply return to this local point with short, low-impedance wiring.
  • Bring STM32/digital ground to the DAC board only as the digital interface reference; do not route STM32/USB return current through OPA signal ground.
  • If supplies are earth-referenced, check for hum loops before connecting the audio amplifier and USB PC simultaneously.
  • On perfboard, consider adding a short tinned-copper ground bus or copper tape ground reference near the analog stages rather than relying on scattered pad-to-pad jumpers.
Power Supply Strategy
  • Use LT3042 3.3 V for PCM1795 digital/control supply.
  • Use LT3042 5 V for PCM1795 analog supply; do not share this rail with the STM32 board load.
  • Use +12 V / −12 V for OPA1612 analog rails.
  • Decouple PCM1795 digital rail with 100 nF + 10 µF near pins.
  • Decouple PCM1795 analog rail with 100 nF + 10 µF + 47 µF near pins.
  • Decouple each OPA1612 package with 100 nF per rail + 10 µF local reservoir; add 100–220 µF bulk per analog rail near card power entry.
  • Bring rails up with current limiting and no audio load first.
Measurement Plan
  1. Power rails only: verify +3.3 V, +5 V, +12 V, −12 V polarity, ripple, and current draw.
  2. No DAC connected to OPA: verify op-amp supply current and output DC offset / oscillation.
  3. Digital only: verify I2S clocks at the DAC adapter before enabling analog chain.
  4. One I/V channel first: verify waveform before building/connecting all four I/V phases.
  5. DAC muted: confirm analog outputs do not show excessive clock feedthrough.
  6. Low-level sine: check OPA outputs for oscillation with oscilloscope bandwidth limit off, then on.
  7. Noise/hum: test with STM32 USB connected vs disconnected and amplifier connected vs disconnected.
Open Data Needed
  • Exact STM32F407 board model and chosen I2S/SPI GPIO pins.
  • PCM1795 adapter pin-1 orientation and continuity confirmation to breakout pads.
  • Linear supply output voltages, current limits, and whether their 0 V outputs connect to earth/chassis.
  • Desired analog output topology: RCA only, balanced output, headphone/line driver, or multiple outputs.
  • Observations From Uploaded Prototype Photos

  • Confirmed From Uploaded Schematic PDF

  • Priority Rules

  • Recommended Wiring For This Perfboard Prototype

  • Grounding Strategy

  • Power Supply Strategy

  • Measurement Plan

  • Open Data Needed

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STM32F407 PCM1795 DAC Interconnect

Properties

Properties describe core aspects of the project.

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