I’ll rebuild this as a real IC-level DAC schematic: PCM1795 pins, three OPA1612 dual op-amps, I/V parts, differential outputs, regulators/connectors, then verify ERC before stopping at the schematic stage.
Rebuilt the project as a real IC-level schematic instead of connector blocks: PCM1795, 3× OPA1612, LT3042 3.3 V/5 V rails, I/V feedback networks, differential output stage, RCA outputs, and power/input headers are now present and wired. ERC checks are currently clean for the checks run, and the project spec was updated.
Open items:
The PCB layout is not done yet; per workflow, this is the schematic checkpoint before layout.
The PCM1795 library symbol/footprint must be visually checked against the TI datasheet pinout before fabrication.
STM32F407 exact I2S/SPI GPIO mapping is still your next firmware/pinout decision.
Suggested next steps:
Review the schematic view and confirm it now looks like the detailed circuit you expected.
I can next create the physical PCB placement with DAC + OPA stages tightly clustered.
After placement approval, I can route the board with low-noise analog layout rules.
LT3042 3.3 V digital DAC rail and LT3042 5 V analog DAC rail.
8-pin power input header for raw DAC regulator inputs, ±12 V OPA rails, GND, and AGND.
RCA left/right output connectors.
Main Signal Chain
Diagram
Key Component Values
Table
Function
Value
I/V feedback RF
680 Ω 0.1%
I/V feedback CF
47 pF C0G/NP0 starting value
I/V non-inverting bias
680 Ω to AGND
Differential output network
10 kΩ 0.1% matched resistors
Differential HF cap
220 pF C0G/NP0
RCA output isolation
100 Ω series
Optional output RF shunt
2.2 nF
I2S/SCK damping
27 Ω starting value
PCM1795 digital rail
3.3 V LT3042
PCM1795 analog rail
5.0 V LT3042
OPA rails
±12 V from LT3045/LT3094 module
Important Caveat
The library PCM1795 symbol must be visually checked against the TI datasheet before PCB layout because the uploaded datasheet pinout is the authority for physical pin numbers. The schematic uses named pins, but any library symbol/footprint mismatch must be corrected before fabrication.
Next Stage
Before PCB layout, verify the schematic visually in Flux and resolve ERC findings. Then proceed to placement with strict analog layout constraints: shortest I/V paths, DAC/OPA clustering, clean AGND/DGND reference join, and physical separation from I2S/SCK lines.