QFN Footprint Paste Fix

A

adrian95

Fix this issue: Footprint QFN50P600X600X100-41N-D for SOT618-1 uses a single full-area 4.25 x 4.25 mm F.Paste opening on exposed pad 41. NXP SOT618-1 recommended reflow footprint specifies a segmented 3x3 array of 0.60 x 0.60 mm paste apertures (2.40 x 2.40 mm overall) and a…

flux

This requires Agent mode to edit the footprint. I’ll replace pad 41’s full-area paste opening with the specified 3×3 array of 0.60 × 0.60 mm apertures, verify the geometry, and file a library-part quality report so the source footprint can be corrected.
Continue in Agent Mode

flux

I’ll inspect pad 41’s current footprint geometry, replace the single paste opening with the specified 3×3 aperture pattern, verify the result, and report the source-part defect.

flux

The full-area paste opening is suppressed and the 3×3 aperture array is in place. I’m checking the final geometry and pad validity now.

flux

The source-part defect report is filed. Final validation is checking that the nine apertures are correctly placed and do not create invalid-pad errors.

flux

Fixed the exposed-pad stencil pattern:
  • Suppressed pad 41’s original 4.25 × 4.25 mm paste opening.
  • Added a centered 3×3 array of 0.60 × 0.60 mm apertures at 0.90 mm pitch, spanning 2.40 × 2.40 mm.
  • Preserved the full exposed-pad copper and solder-mask geometry.
  • Filed an internal quality report for correction of the source library footprint.
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Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
DVSS
1
Ground
Ground
Ground
Bottom
10
LOADMOD
2
Output
RF
RF
Left
1
TVSS1
3
Ground
Ground
Ground
Bottom
11
TX1
4
Output
RF
RF
Left
2
TVDD
5
Power In
Power
Power
Top
1
TX2
6
Output
RF
RF
Left
3
TVSS2
7
Ground
Ground
Ground
Bottom
12
AVDD
8
Power In
Power
Power
Top
2
VMID
9
Output
RF
RF
Left
4
RX
10
Input
RF
RF
Left
5
AVSS
11
Ground
Ground
Ground
Bottom
13
AUX1
12
Output
Analog/Auxiliary
Analog/Auxiliary
Right
1
AUX2
13
Output
Analog/Auxiliary
Analog/Auxiliary
Right
2
OSCIN
14
Input
Clock
Clock
Left
1
OSCOUT
15
Output
Clock
Clock
Left
2
I0
16
Input
Interface Selection
Interface Selection
Left
1
I1
17
Input
Interface Selection
Interface Selection
Left
2
TESTEN
18
Input
Test
Test
Left
1
P35
19
Bi-Directional
GPIO/UART
GPIO/UART
Right
1
N.C._1
20
Not Connected
NC
NC
Right
1
N.C._2
21
Not Connected
NC
NC
Right
2
N.C._3
22
Not Connected
NC
NC
Right
3
PVDD
23
Power In
Power
Power
Top
3

PN5321A3HN/C106,51