Part Audit Review

A

adrian95

Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.

flux

I’ll audit the part metadata, source the official datasheet if needed, update its Datasheet property, then verify the symbol, footprint, and pin descriptions against the manufacturer documentation.

flux

The part already has a Datasheet URL, but it points to a third-party archive. I found the current official Microchip datasheet and am using that as the verification source; the metadata and footprint have already exposed several likely classification and geometry issues.
Created a project doc

PIC18F26K22-I/SS Part Audit

View Document
Official manufacturer datasheet: https://ww1.microchip.com/downloads/aemDocuments/documents/MCU08/ProductDocuments/DataSheets/PIC18%28L%29F2...

flux

Audit complete. Pin numbering and footprint mapping are correct, but the part has incorrect MCU classification (Logic / AND), an inaccurate RAM description, missing pin types/descriptions and alternate functions, plus ambiguous SSOP package metadata; the existing Datasheet URL was already populated, so it was not changed.
Full findings and recommended corrections: PIC18F26K22-I/SS Part Audit.
Fix metadata and pins
Update datasheet URL
Validate footprint dimensions
Run part review
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PIC18F26K22-I/SS Part Audit
Verification source
Available part information

Table

FieldCurrent valueAudit result
MPNPIC18F26K22-I/SSCorrect
ManufacturerMicrochipCorrect; preferred full name is Microchip Technology
DescriptionMCU, 64KB, 3968b-RAM, Flash,nanoWatt XLPPartially incorrect: SRAM is 3896 bytes, not 3968 bits/bytes; wording is ambiguous and omits key features
Pin count28Correct
PackageNot present as a part property; footprint named SOP65P780X200-28NMPN suffix /SS means 28-lead SSOP, 0.65 mm pitch; package property should explicitly say SSOP-28
Part TypeIntegrated CircuitsBroad but acceptable
IC subtypeLogicIncorrect; this is an 8-bit microcontroller
Logic functionANDIncorrect and unrelated
Designator prefixICAcceptable, though U is also conventional
Datasheet URLThird-party archive URLURL exists, but official Microchip URL is preferable
Key specifications
  • 8-bit PIC18 high-performance RISC microcontroller with nanoWatt XLP technology.
  • 64 KB Flash program memory; 32,768 single-word instruction capacity.
  • 3,896 bytes SRAM/data memory.
  • 1,024 bytes data EEPROM.
  • DC to 64 MHz operation.
  • 25 GPIO pins, including one input-only RE3 function.
  • 19 ADC channels total including internal FVR and DAC channels; 10-bit ADC.
  • Two MSSP blocks supporting SPI/I2C, two EUSARTs, two comparators, CTMU, DAC/FVR, CCP/ECCP modules, three 8-bit timers, and four 16-bit timers.
  • I temperature grade: -40 °C to +85 °C.
  • /SS package: 28-lead SSOP.
  • PIC18F26K22 absolute VDD rating: -0.3 V to +6.5 V; operating use must remain within datasheet DC-characteristic limits. Maximum I/O source or sink rating is 25 mA per pin, subject to aggregate port/device limits.
Schematic symbol audit
Correct items
  • Exactly 28 terminals are present.
  • Physical pin numbering matches the official 28-pin PDIP/SOIC/SSOP diagram:
    • 1 MCLR/VPP/RE3
    • 2-7 RA0-RA5
    • 8 VSS
    • 9 RA7, 10 RA6
    • 11-18 RC0-RC7
    • 19 VSS, 20 VDD
    • 21-28 RB0-RB7
  • RB6/PGC and RB7/PGD are mapped to pins 27 and 28 correctly.
Mismatches / omissions
  • Every terminal has Pin Type = Unspecified. Power, ground, input, and bidirectional I/O types should be assigned for ERC quality.
  • No terminal has a meaningful Pin Description.
  • Most terminal names show only the basic GPIO name and omit datasheet multiplexed functions. Examples:
    • Pin 2 should include RA0/C12IN0-/AN0.
    • Pin 4 should include RA2/C2IN+/AN2/DACOUT/VREF-.
    • Pin 9 should include RA7/CLKI/OSC1.
    • Pin 10 should include RA6/CLKO/OSC2.
    • Pin 21 should include RB0/INT0/CCP4/FLT0/SRI/SS2/AN12.
    • Pin 27 should include RB6/IOC2/TX2/CK2/PGC.
    • Pin 28 should include RB7/IOC3/RX2/DT2/PGD.
    • RC0-RC7 similarly omit timer, PWM/CCP, MSSP, EUSART, oscillator, and analog functions.
  • Pin 1 contains the correct three primary functions, but its ordering differs from the datasheet (RE3/VPP/MCLR); this is not an electrical error.
  • The symbol is therefore electrically number-correct but documentation-poor and less useful for peripheral selection.
Footprint audit
Geometry and mapping
  • The footprint contains 28 SMD pads with 0.65 mm pitch.
  • Raw footprint geometry indicates approximately 5.3 mm body width, 10.2 mm body length, 7.1 mm pad-center span, and 7.8 mm nominal overall package span naming (SOP65P780X200-28N). These values are consistent with the common Microchip 28-lead SSOP family outline.
  • Pads are 0.45 mm x 1.8 mm and numbered in standard counter-clockwise IC order.
  • Symbol-to-pad physical pin mapping is correct.
  • Pin-1 marking exists on fabrication and silkscreen layers.
Mismatches / risks
  • The footprint source description says PIC18F24J50-I/SS-1, not PIC18F26K22-I/SS. The package geometry may be reusable and appears compatible, but the embedded description is incorrect provenance/metadata.
  • The footprint is named SOP... rather than explicitly SSOP-28; this is naming ambiguity rather than a demonstrated dimensional error.
  • No explicit package/case property ties the MPN suffix /SS to the footprint.
  • The footprint inspection output shows converted computed coordinates at 0.001 scale while the raw KiCad payload is in correct millimetres. The raw payload should be treated as the geometry source; a visual/3D scale check is still advisable before publishing.
  • The datasheet delegates current package drawings to Microchip's packaging specification. The footprint appears dimensionally plausible, but a final production release should compare it against the latest Microchip SS package drawing and land-pattern recommendation.
Overall assessment
Electrical pin numbering and pad mapping are correct. The main defects are inaccurate metadata, missing pin descriptions/types, omitted alternate pin functions, and ambiguous package metadata. The footprint geometry appears suitable for a 28-lead 0.65 mm-pitch SSOP, but its embedded source description references a different MCU and should be cleaned up or independently validated against the latest Microchip package drawing.
  1. Replace the description with: 8-bit PIC18 MCU, 64 KB Flash, 3,896 B SRAM, 1,024 B EEPROM, 64 MHz, nanoWatt XLP, 28-SSOP.
  2. Change IC subtype from Logic to Microcontroller and remove Logic Function = AND.
  3. Add Package or Case Code = SSOP-28 (0.65 mm pitch).
  4. Prefer the official Microchip datasheet URL above.
  5. Populate every terminal's complete multiplexed pin name, Pin Description, and appropriate Pin Type.
  6. Correct the footprint description/provenance and verify the current Microchip 28-lead SSOP package/land-pattern drawing before manufacturing release.

  • Verification source

  • Available part information

  • Key specifications

  • Schematic symbol audit

  • Correct items

  • Mismatches / omissions

  • Footprint audit

  • Geometry and mapping

  • Mismatches / risks

  • Overall assessment

  • Recommended corrections