ESP32-C5-Zero Audit
Thought for 30 sec
I’ll incorporate this into the audit using the current part, ESP32-C5-Zero, as the target MPN. I’ll preserve every existing pin number and mapping, assign datasheet-backed descriptions/types plus balanced symbol orientation and ordering, remove any Pin Group properties, and then verify the result.
Worked for 3 mins 15 sec
Created a project doc
ESP32-C5-Zero Part Audit
Waveshare product documentation: https://docs.waveshare.com/ESP32-C5-Zero Waveshare hardware resources: https://docs.waveshare.com/ESP32-C5-...
Updated all 18 symbol terminals against Waveshare’s official ESP32-C5-Zero documentation: pin mappings were preserved, Pin Group was removed, descriptions/types were corrected, and sections/orientations/orders were balanced with power first and ground last.
The full specifications, footprint comparison, sources, and flagged metadata/mechanical risks are in ESP32-C5-Zero Part Audit. The part-level Datasheet property was not exposed for safe editing; the recommended URL is
https://docs.waveshare.com/ESP32-C5-Zero.Fix metadata and geometry
Set part metadata
Validate footprint geometry
Review ERC DRC
Check hidden pads
Refine this doc
Ask about this doc
ESP32-C5-Zero Part Audit
Sources
- Waveshare product documentation: https://docs.waveshare.com/ESP32-C5-Zero
- Waveshare hardware resources: https://docs.waveshare.com/ESP32-C5-Zero/Resources-And-Documents
- Official Waveshare schematic: https://raw.githubusercontent.com/waveshareteam/ESP32-C5-Zero/main/hardware/schematics/ESP32-C5-Zero.pdf
- Official Waveshare mechanical drawing: https://raw.githubusercontent.com/waveshareteam/ESP32-C5-Zero/main/hardware/dimensions/esp32-c5-zero-Size.pdf
- Espressif ESP32-C5 datasheet: https://documentation.espressif.com/esp32-c5_datasheet_en.pdf
Identified Part
- Manufacturer: Waveshare
- MPN/model: ESP32-C5-Zero, without pre-soldered headers; ESP32-C5-Zero-M is the header-equipped variant
- Waveshare SKU: 34599 for ESP32-C5-Zero; 34598 for ESP32-C5-Zero-M
- Form factor: 18-pad castellated development-board module
- Mechanical outline: 18.00 mm x 28.00 mm
- External pad pitch: 2.54 mm
- Processor: ESP32-C5-HF4, 32-bit high-performance RISC-V core up to 240 MHz
- Memory: 4 MB in-package flash, 384 KB HP SRAM plus 16 KB LP SRAM, 320 KB ROM
- Wireless: 2.4/5 GHz Wi-Fi 6, Bluetooth LE, IEEE 802.15.4 supporting Zigbee and Thread
- Interfaces/features: USB-C, USB Serial/JTAG on GPIO13/14, UART0 on GPIO11/12, six 12-bit ADC channels on GPIO1-GPIO6, ceramic antenna and IPEX-1 selection, onboard WS2812
Pin Mapping Cross-check
The existing schematic and footprint both contain 18 terminals/pads. Existing pin numbers and mappings match the official board pinout under the standard counter-clockwise module numbering convention:
Table
| Pin | Existing name | Official function |
|---|---|---|
| 1 | 5V | 5 V board power input |
| 2 | GND | Ground |
| 3 | 3V3(OUT) | Regulated 3.3 V output |
| 4 | GP0 | GPIO0 |
| 5 | GP1 | GPIO1 / ADC1_CH0 |
| 6 | GP2 | GPIO2 / ADC1_CH1 |
| 7 | GP3 | GPIO3 / ADC1_CH2 |
| 8 | GP4 | GPIO4 / ADC1_CH3 |
| 9 | GP5 | GPIO5 / ADC1_CH4 |
| 10 | GP6 | GPIO6 / ADC1_CH5 |
| 11 | GP7 | GPIO7 |
| 12 | GP8 | GPIO8 |
| 13 | GP9 | GPIO9 |
| 14 | GP10 | GPIO10 |
| 15 | GP14 | GPIO14 / USB D+ |
| 16 | GP13 | GPIO13 / USB D- |
| 17 | GP12 | GPIO12 / UART0 RX |
| 18 | GP11 | GPIO11 / UART0 TX |
Applied Symbol Corrections
- Preserved all 18 pin numbers, names, and footprint mappings.
- Removed
Pin Groupfrom every terminal. - Assigned Power, GPIO, and Ground sections.
- Assigned terminal order 1-18, placing power first and ground last.
- Balanced the GPIO section as seven pins on the left and eight on the right.
- Placed the two power pins on opposite sides and the singleton ground pin on the bottom.
- Assigned electrical types and datasheet-backed pin descriptions.
Footprint Review
- Pad count matches: 18.
- Main footprint outline matches the official nominal 18 mm x 28 mm module dimensions.
- The footprint drawing includes the USB-C end outline and a pin-1 marker near the top-left/5V corner.
- The official size drawing confirms 2.54 mm pad pitch.
- Exact castellated land width, half-hole diameter, annulus, and row center spacing are not fully dimensioned in the public size PDF. The official DXF/STEP files should be treated as the final mechanical authority for production land-pattern verification.
Mismatches and Risks
- Metadata incompleteness: The accessible part data does not expose a populated part-level MPN, manufacturer, package/case, or Datasheet URL property, even though the project name and description identify the board.
- Datasheet property: An official documentation source was found, but the available editor exposes only terminal-level component properties in this part project; no safe part-level Datasheet property target was available. The recommended Datasheet URL is
https://docs.waveshare.com/ESP32-C5-Zero, with the Espressif chip datasheet retained as a secondary technical source. - Footprint precision: Nominal outline and pitch agree, but exact pad geometry could not be conclusively validated from the public dimension PDF alone. Compare/import the official DXF before releasing a carrier-board footprint for manufacturing.
- Pin naming style: Official documentation uses GPIO terminology, while the symbol uses
GPx. The mapping is correct, so names were not changed per the no-renumber/no-remap constraint. - Additional board pads: Waveshare documentation shows additional back-side test/castellated contacts GP23, GP24, GP25, and GP28 on the physical board. They are not part of the standard 18 edge-pad interface represented by this part; confirm whether the intended footprint should expose them before adding any pads.
Result
The 18-pin schematic symbol is now ordered and annotated consistently with the official Waveshare pinout. No pin-number or mapping mismatch was found in the represented 18-pad interface. The remaining concerns are part-level metadata population and production-grade validation of exact castellated land geometry against the official DXF.
Sources
Identified Part
Pin Mapping Cross-check
Applied Symbol Corrections
Footprint Review
Mismatches and Risks
Result
