ESP32-C5-Zero Audit

C

cherepanyadima

Check this schematic component against the datasheet for [MPN] and assign the correct pin orientation, section, and terminal order without changing, replacing, renumbering, or remapping any pins. Remove the Pin Group property from all pins if it exists. Place Power pins first and Ground pins last. Within each section, distribute the pins as evenly as possible between the left and right sides; for example, split 10 pins as 5/5 and 11 pins as 5/6 or 6/5. If a section contains only one pin, leave it on the most appropriate side. Keep the symbol compact, balanced, and visually symmetrical. If a pin function is unclear, assign Unclear / Check datasheet, then apply all changes directly to the schematic component.

flux

I’ll incorporate this into the audit using the current part, ESP32-C5-Zero, as the target MPN. I’ll preserve every existing pin number and mapping, assign datasheet-backed descriptions/types plus balanced symbol orientation and ordering, remove any Pin Group properties, and then verify the result.
Created a project doc

ESP32-C5-Zero Part Audit

View Document
Waveshare product documentation: https://docs.waveshare.com/ESP32-C5-Zero Waveshare hardware resources: https://docs.waveshare.com/ESP32-C5-...

flux

Updated all 18 symbol terminals against Waveshare’s official ESP32-C5-Zero documentation: pin mappings were preserved, Pin Group was removed, descriptions/types were corrected, and sections/orientations/orders were balanced with power first and ground last.
The full specifications, footprint comparison, sources, and flagged metadata/mechanical risks are in ESP32-C5-Zero Part Audit. The part-level Datasheet property was not exposed for safe editing; the recommended URL is https://docs.waveshare.com/ESP32-C5-Zero.
Fix metadata and geometry
Set part metadata
Validate footprint geometry
Review ERC DRC
Check hidden pads
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ESP32-C5-Zero Part Audit
Sources
Identified Part
  • Manufacturer: Waveshare
  • MPN/model: ESP32-C5-Zero, without pre-soldered headers; ESP32-C5-Zero-M is the header-equipped variant
  • Waveshare SKU: 34599 for ESP32-C5-Zero; 34598 for ESP32-C5-Zero-M
  • Form factor: 18-pad castellated development-board module
  • Mechanical outline: 18.00 mm x 28.00 mm
  • External pad pitch: 2.54 mm
  • Processor: ESP32-C5-HF4, 32-bit high-performance RISC-V core up to 240 MHz
  • Memory: 4 MB in-package flash, 384 KB HP SRAM plus 16 KB LP SRAM, 320 KB ROM
  • Wireless: 2.4/5 GHz Wi-Fi 6, Bluetooth LE, IEEE 802.15.4 supporting Zigbee and Thread
  • Interfaces/features: USB-C, USB Serial/JTAG on GPIO13/14, UART0 on GPIO11/12, six 12-bit ADC channels on GPIO1-GPIO6, ceramic antenna and IPEX-1 selection, onboard WS2812
Pin Mapping Cross-check
The existing schematic and footprint both contain 18 terminals/pads. Existing pin numbers and mappings match the official board pinout under the standard counter-clockwise module numbering convention:

Table

PinExisting nameOfficial function
15V5 V board power input
2GNDGround
33V3(OUT)Regulated 3.3 V output
4GP0GPIO0
5GP1GPIO1 / ADC1_CH0
6GP2GPIO2 / ADC1_CH1
7GP3GPIO3 / ADC1_CH2
8GP4GPIO4 / ADC1_CH3
9GP5GPIO5 / ADC1_CH4
10GP6GPIO6 / ADC1_CH5
11GP7GPIO7
12GP8GPIO8
13GP9GPIO9
14GP10GPIO10
15GP14GPIO14 / USB D+
16GP13GPIO13 / USB D-
17GP12GPIO12 / UART0 RX
18GP11GPIO11 / UART0 TX
Applied Symbol Corrections
  • Preserved all 18 pin numbers, names, and footprint mappings.
  • Removed Pin Group from every terminal.
  • Assigned Power, GPIO, and Ground sections.
  • Assigned terminal order 1-18, placing power first and ground last.
  • Balanced the GPIO section as seven pins on the left and eight on the right.
  • Placed the two power pins on opposite sides and the singleton ground pin on the bottom.
  • Assigned electrical types and datasheet-backed pin descriptions.
Footprint Review
  • Pad count matches: 18.
  • Main footprint outline matches the official nominal 18 mm x 28 mm module dimensions.
  • The footprint drawing includes the USB-C end outline and a pin-1 marker near the top-left/5V corner.
  • The official size drawing confirms 2.54 mm pad pitch.
  • Exact castellated land width, half-hole diameter, annulus, and row center spacing are not fully dimensioned in the public size PDF. The official DXF/STEP files should be treated as the final mechanical authority for production land-pattern verification.
Mismatches and Risks
  1. Metadata incompleteness: The accessible part data does not expose a populated part-level MPN, manufacturer, package/case, or Datasheet URL property, even though the project name and description identify the board.
  2. Datasheet property: An official documentation source was found, but the available editor exposes only terminal-level component properties in this part project; no safe part-level Datasheet property target was available. The recommended Datasheet URL is https://docs.waveshare.com/ESP32-C5-Zero, with the Espressif chip datasheet retained as a secondary technical source.
  3. Footprint precision: Nominal outline and pitch agree, but exact pad geometry could not be conclusively validated from the public dimension PDF alone. Compare/import the official DXF before releasing a carrier-board footprint for manufacturing.
  4. Pin naming style: Official documentation uses GPIO terminology, while the symbol uses GPx. The mapping is correct, so names were not changed per the no-renumber/no-remap constraint.
  5. Additional board pads: Waveshare documentation shows additional back-side test/castellated contacts GP23, GP24, GP25, and GP28 on the physical board. They are not part of the standard 18 edge-pad interface represented by this part; confirm whether the intended footprint should expose them before adding any pads.
Result
The 18-pin schematic symbol is now ordered and annotated consistently with the official Waveshare pinout. No pin-number or mapping mismatch was found in the represented 18-pad interface. The remaining concerns are part-level metadata population and production-grade validation of exact castellated land geometry against the official DXF.

  • Sources

  • Identified Part

  • Pin Mapping Cross-check

  • Applied Symbol Corrections

  • Footprint Review

  • Mismatches and Risks

  • Result