Part Audit Review


Reorganized all 95 CMV2000-2E5M1LP terminals into seven datasheet-backed sections. Power is first, Ground last, and each section is evenly balanced left/right with unique terminal ordering.
  • Pin Group removed from every terminal.
  • No pins were renamed, replaced, renumbered, deleted, or remapped.
  • All 95 package coordinates remain unchanged and unique.
  • No unclear pin functions were found.
Official ams OSRAM DS000734 v8-00 shows principal ceramic LGA body outline 13.50 x 16.50 mm, but the Flux footprint fabrication/silkscreen outline is 13.50 x 18.65 mm and courtyard is correspondingly oversized.
check and correct if necessary according to the datasheet
I’ll verify the DS000734 v8-00 mechanical drawing and current footprint dimensions, then correct only the body-related fabrication, silkscreen, and courtyard geometry if the 18.65 mm extent is unsupported.
The datasheet confirms 18.65 mm belongs to the µPGA lead-related overall extent, not the ceramic LGA body. I’ve corrected the footprint asset to the 13.50 × 16.50 mm body and retained its existing 1.00 mm courtyard margin; now I’m verifying the loaded footprint and all 95 pads.
Verification passed: the corrected asset contains 95 pads with the same grid, omitted A1, 0.300 mm lands, pin-1 marker, and STEP reference; only the body and courtyard Y extents changed.
Corrected the footprint per ams OSRAM DS000734 v8-00:
  • F.Fab / F.SilkS: 13.50 × 16.50 mm
  • F.CrtYd: 15.50 × 18.50 mm, retaining the original 1.00 mm margin
  • Unchanged: all 95 pads, numbering/mapping, 1.27 mm grid, 0.300 mm lands, pin-1 marker, and STEP model
The 18.65 mm dimension applies to the µPGA lead-related extent, not the LGA ceramic body. I also filed a library part-quality report with Flux.

A7 · VDD20_1C7 · VDD20_2E4 · VDD20_3E2 · VDD33_1E6 · VDDPIX_1F7 · VRES_HVDD20_4 · E7VDD20_5 · E8VDD33_2 · H1VDD33_3 · H6VDDPIX_2 · G1VDDPIX_3 · G12G10 · ADCG6 · CMD_NG9 · COL_AMPH10 · COL_PCF10 · RAMPE10 · SG_ADCF6 · VPCH_HE12 · VRAMP2H8 · VRES_LF8 · VTF_L2CMD_P · G5CMD_P__INV · F5COL_LOAD · F9LVDS · H11REF_ADC · D12VBGAP · G11VRAMP1 · E11VREF · D11VTF_L1_ · G8VTF_L3 · H9E1 · CLK_INF2 · FRAME__REQH5 · SYS__RES_NH3 · T_EXP1G3 · T_EXP2SPI_EN · G4SPI_CLK · H4SPI_IN · F3SPI_OUT · F4D2 · LVDS__CLK_NLVDS__CLK_P · D1B11 · OUT_CLK_NB1 · OUT_CTR_NC2 · OUT1_NA2 · OUT2_ND3 · OUT3_NB3 · OUT4_NA4 · OUT5_NC4 · OUT6_NB5 · OUT7_ND5 · OUT8_ND7 · OUT9_NB7 · OUT10_NC8 · OUT11_NA8 · OUT12_NB9 · OUT13_ND9 · OUT14_NA10 · OUT15_NC10 · OUT16_NOUT_CLK_P · B12OUT_CTR_P · B2OUT1_P · C3OUT2_P · A3OUT3_P · D4OUT4_P · B4OUT5_P · A5OUT6_P · C5OUT7_P · B6OUT8_P · D6OUT9_P · D8OUT10_P · B8OUT11_P · C9OUT12_P · A9OUT13_P · B10OUT14_P · D10OUT15_P · A11OUT16_P · C11G7 · TANAH2 · TDIG1TDIG2 · G2DIO1 · F11DIO2 · H12A6 · GND_1A12 · GND_2C1 · GND_3C6 · GND_4C12 · GND_5GND_6 · E3GND_7 · E5GND_8 · E9GND_9 · F1GND_10 · F12GND_11 · H7

CMV2000-2E5M1LP