修正PCB短路与浮铜
Worked for 4 mins 46 sec
已按“模块接口”完成输出级原理图骨架，没有放入任何错误的三脚 MOSFET 替代件。
已添加并连接：
CELL_DC_P / CELL_DC_N：输出单元直流母线接口CELL_OUT：半桥/多电平单元输出节点HS_GATE / HS_KS：高边未来 CI90N120SM4 的 Gate / Kelvin Source 接口LS_GATE / LS_KS：低边未来 CI90N120SM4 的 Gate / Kelvin Source 接口HS_GATE_DRV / LS_GATE_DRV：栅极驱动输入接口RGH_CELL / RGL_CELL = 2.5Ω：门极串联电阻占位RGH_PD / RGL_PD = 10kΩ：Gate-Kelvin Source 下拉CDCELL_HF = 100nF / 1200V：输出单元高频母线旁路占位
检查结果：原理图接口网络已建立；当前报错主要是 PCB 尚未为新增模块接口放置/布线产生的 airwires，以及已有布局中的一个 overlapping copper。下一步应导入/创建 CI90N120SM4 四引脚器件 后，把这些接口替换为真实 MOSFET 符号并继续完善栅极驱动和保护。
备选方案 Microchip MSC025SMA120B4N怎么样
Thought for 33 sec
我会把 Microchip MSC025SMA120B4N 作为非国产备选来评估：重点核对耐压、电流、RDS(on)、Qg、Kelvin 源极、驱动电压和开关损耗，再判断是否适合作为临时原理图器件或最终备选。
Working for 3 days 1 hr...
Thought for 6 sec
Reading MSC025SMA120B4N datasheet for absolute maximum ratings VDS VGS continu.
Reading MSC025SMA120B4N datasheet for electrical characteristics RDS on gate t.
Reading MSC025SMA120B4N datasheet for switching characteristics turn on energy.
Reading MSC025SMA120B4N datasheet for pin configuration package TO-247-4 Kelvi...
与外界的联系只有供电输入，信号输入输出
Pulling up the datasheet...
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PCB Routing Order Recommendation
Current PCB State
- Board: 120 mm × 80 mm rectangle.
- Stackup: 4 copper layers.
- Placed components: 50 functional components, all on top layer.
- Component density: low, about 14.3% component-area fill.
- Routing congestion: low; board has enough room for staged routing.
- Current DRC focus result: 75 airwires remain. No overlapping-copper, floating-copper, dangling-trace, overlapping-trace, or invalid-layer issues were reported in the checked categories.
Functional Placement Summary
The placement is already separated in a left-to-right power-flow style:
- Left/input side:
- J1, J4 input terminal blocks
- F1 fuse
- RV1 MOV
- BR1 bridge rectifier
- CX1, RCX1 input suppression/snubber area
- Center:
- T1 transformer
- CBUS1/CBUS2 DC bus bulk capacitors
- RHV_IN_POS/RHV_IN_NEG and bus-related resistors
- Right/output/control side:
- J5 output connector
- HV rectifier/diode and capacitor network: DVP1/DVP2/DVN1/DVN2, CHVP1/CHVN1, CHV_POS/CHV_NEG
- Feedback divider chains: R1-R6, RFB1/RFB5/RFB6/RFB10, R2/R3/R4/R5/R6
- Over-current comparator section: UOC1, RSH1, ROC_IN, ROC_REF_TOP/BOT, ROC_HYS, ROC_PULLUP, COC_DEC/COC_IN/COC_REF
Recommended Layer Strategy
Use the 4-layer board as follows:
- Layer 1 / Top: primary component-side routing, especially short local connections.
- Layer 2 / Inner 1: keep as the main ground/return reference plane where possible.
- Layer 3 / Inner 2: use for power distribution or long non-sensitive power interconnects when needed.
- Layer 4 / Bottom: secondary routing for crossings and signal escape.
Avoid splitting the ground return path under control/comparator traces. For high-voltage sections, prioritize creepage/clearance and keep HV positive/negative routing physically separated from low-voltage control routing.
Recommended Routing Order
0. Pre-routing cleanup gate
Before routing, re-run checks for:
- dangling traces
- overlapping copper
- invalid layers
- existing short/overlap issues
Only start routing if these are clean. Current checked categories are clean except airwires.
1. Safety and high-energy input path first
Route these before small-signal nets:
- AC_L
- AC_N
- AC_L_FUSED
- HV_DC_POS
- HV_DC_NEG
Suggested handling:
- Use wider traces or copper areas where current is high.
- Keep AC input and rectified DC bus away from comparator/control nets.
- Keep J1/J4 -> F1/RV1/BR1 paths direct and mechanically obvious.
- Keep MOV and fuse connections short and robust.
2. Transformer primary and HV switching/drive path
Route the primary-side transformer nets next:
- PRI_90-375V_65KHZ_1 related airwires
- Net 3 / Net 4 if they are part of the reconstructed transformer or bus loop
Suggested handling:
- Keep the primary loop compact.
- Avoid routing sensitive comparator/reference traces through this area.
- Preserve isolation spacing around T1, especially between primary-side and secondary-side pads.
3. Secondary HV output rectifier and energy path
Route the high-voltage secondary and rectifier/output energy nets next:
- HV_SEC_POS_AC
- HV_SEC_NEG_AC
- HV_POS_BUS
- HV_NEG_BUS
- HV_RET
- VFB_P / VFB_N only where they are physically tied to the output/feedback pickoff
Suggested handling:
- Route DVP/DVN diode paths and CHVP/CHVN capacitors with short, direct loops.
- Keep HV_POS_BUS and HV_NEG_BUS well separated.
- Use the output connector J5 orientation as the endpoint; route output energy paths before feedback dividers.
- Avoid running low-voltage control traces between HV bus conductors.
4. Bleeder/discharge and HV sense chains
Route high-value resistor chains after the main HV buses:
- RHV_BLEED_POS
- RHV_BLEED_NEG
- RHVP_DIS
- RHVN_DIS
- VFBP_DIV1
- VFBP_DIV2
- VFBP_DIV3
- VFBN_DIV1
- VFBN_DIV2
- VFBN_DIV3
Suggested handling:
- Keep divider chains physically linear and away from noisy primary switching areas.
- Maintain clearance between adjacent high-voltage nodes across the divider.
- Avoid placing control traces under or between high-voltage divider nodes.
5. Comparator power and reference network
Route clean low-voltage rails/reference next:
- 5V_CTRL
- AGND
- OC_REF_0V3
Suggested handling:
- Route UOC1 decoupling capacitor COC_DEC very short to the comparator power/ground pins.
- Keep ROC_REF_TOP, ROC_REF_BOT, COC_REF close to UOC1.
- Use a quiet AGND return for comparator/reference components; avoid sharing high-current HV return segments.
6. Current-sense and over-current signal path
Route current-sense/control nets next:
- OC_SENSE
- OC_TRIP_N
- IN_PLUS
- IN_MINUS
Suggested handling:
- Keep RSH1 sense path short and Kelvin-like if possible.
- Route IN_PLUS/IN_MINUS as a quiet local pair into UOC1.
- Keep OC_TRIP_N away from high-voltage/high-dvdt paths and avoid long parallel runs next to transformer primary/secondary traces.
7. Remaining low-risk local passives
Route any remaining local passive nets last:
- short local resistor/capacitor links not covered above
- small signal feedback and hysteresis links around UOC1
Suggested handling:
- Prefer top-layer short direct routes where no crossing is needed.
- Use bottom layer only for clean crossings.
- Add GND stitching vias near signal vias if the route changes layer around control signals.
Suggested Automated Routing Batches
If proceeding with automated routing, do it in batches rather than one pass:
- Batch A: AC/input/DC bus/power nets
- AC_L, AC_N, AC_L_FUSED, HV_DC_POS, HV_DC_NEG
- Batch B: transformer and HV output energy nets
- HV_SEC_POS_AC, HV_SEC_NEG_AC, HV_POS_BUS, HV_NEG_BUS, HV_RET
- Batch C: feedback/bleeder/divider nets
- VFBP_DIV1/2/3, VFBN_DIV1/2/3, VFB_P, VFB_N, RHV discharge/bleed nets
- Batch D: comparator/control nets
- 5V_CTRL, AGND, OC_REF_0V3, OC_SENSE, OC_TRIP_N, IN_PLUS, IN_MINUS
- Batch E: all remaining airwires
After each batch, re-run DRC checks for airwires, overlapping copper, clearance, and floating copper before proceeding.
Notes and Risks
- This project was reconstructed from manufacturing data, so routing order is inferred from net names, component values, and placement rather than the original designer's intent.
- High-voltage clearance requirements must be reviewed before final manufacturing. The current recommendation assumes a conservative staged routing flow but does not replace formal safety/creepage calculation.
- The two previously suspicious shorted input resistors were corrected in the logical reconstruction; re-check after routing to ensure no copper reintroduces same-net or unintended bridges.
Current PCB State
Functional Placement Summary
Recommended Layer Strategy
Recommended Routing Order
0. Pre-routing cleanup gate
1. Safety and high-energy input path first
2. Transformer primary and HV switching/drive path
3. Secondary HV output rectifier and energy path
4. Bleeder/discharge and HV sense chains
5. Comparator power and reference network
6. Current-sense and over-current signal path
7. Remaining low-risk local passives
Suggested Automated Routing Batches
Notes and Risks
