修正PCB短路与浮铜
Worked for 4 mins 46 sec
已按“模块接口”完成输出级原理图骨架，没有放入任何错误的三脚 MOSFET 替代件。
已添加并连接：
CELL_DC_P / CELL_DC_N：输出单元直流母线接口CELL_OUT：半桥/多电平单元输出节点HS_GATE / HS_KS：高边未来 CI90N120SM4 的 Gate / Kelvin Source 接口LS_GATE / LS_KS：低边未来 CI90N120SM4 的 Gate / Kelvin Source 接口HS_GATE_DRV / LS_GATE_DRV：栅极驱动输入接口RGH_CELL / RGL_CELL = 2.5Ω：门极串联电阻占位RGH_PD / RGL_PD = 10kΩ：Gate-Kelvin Source 下拉CDCELL_HF = 100nF / 1200V：输出单元高频母线旁路占位
检查结果：原理图接口网络已建立；当前报错主要是 PCB 尚未为新增模块接口放置/布线产生的 airwires，以及已有布局中的一个 overlapping copper。下一步应导入/创建 CI90N120SM4 四引脚器件 后，把这些接口替换为真实 MOSFET 符号并继续完善栅极驱动和保护。
备选方案 Microchip MSC025SMA120B4N怎么样
Thought for 33 sec
我会把 Microchip MSC025SMA120B4N 作为非国产备选来评估：重点核对耐压、电流、RDS(on)、Qg、Kelvin 源极、驱动电压和开关损耗，再判断是否适合作为临时原理图器件或最终备选。
Working for 2 days 17 hrs...
Thought for 6 sec
Reading MSC025SMA120B4N datasheet for absolute maximum ratings VDS VGS continu.
Reading MSC025SMA120B4N datasheet for electrical characteristics RDS on gate t.
Reading MSC025SMA120B4N datasheet for switching characteristics turn on energy.
Reading MSC025SMA120B4N datasheet for pin configuration package TO-247-4 Kelvi...
与外界的联系只有供电输入，信号输入输出
Pulling up the datasheet...
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Project Specification — High Voltage Arbitrary Waveform Amplifier
Purpose
Design a new high-voltage wideband power amplifier. This replaces the previous recovered/manufacturing-data-based flyback ultrasonic pulse board concept; the old T1 flyback topology is not suitable for the new arbitrary-waveform target.
Confirmed User Requirements
Table
| Parameter | Requirement |
|---|---|
| AC input supply | 220 VAC mains |
| Signal input | +/-10 V arbitrary waveform |
| Output voltage | +/-1000 V peak |
| Load | 2.5 nF capacitive load |
| Frequency range | 0 to 500 kHz |
| Output current capability | >=10 A peak |
| Maximum output dv/dt | =10 A peak output capability provides margin above the calculated 7.85 A peak sinusoidal capacitive current requirement. Arbitrary waveforms with faster edges can still require higher instantaneous current because i = C*dv/dt, so the output stage must include current limiting and slew-rate-aware protection. |
Maximum dv/dt Limit
For a capacitive load, current is directly proportional to voltage slew rate:
I = C * dv/dt
Using the confirmed limits:
- Imax = 10 A peak
- Cload = 2.5 nF
The maximum allowable slew rate is:
- dv/dt_max = Imax / Cload = 10 A / 2.5 nF = 4.0e9 V/s = 4000 V/us
Therefore arbitrary output waveforms must be slew-rate limited to =10 A peak output-current target. Faster edges would exceed the output current specification.
Sine-Wave Slew Rate Check
For a sine wave at 500 kHz and 1000 V peak:
SR = 2pif*Vpk
- SR = 2pi500 kHz*1000 V = 3.14e9 V/s = 3140 V/us
This is below the 4000 V/us current-limited dv/dt maximum, so a 500 kHz, +/-1000 Vpeak sine wave is compatible with the 2.5 nF, >=10 A peak target. However, non-sinusoidal arbitrary waveforms must be checked against the 4000 V/us dv/dt limit.
Output Power and Reactive Energy
The load is primarily capacitive. The instantaneous current can be high even if average real power depends on load loss and energy recovery. The output stage and supply must be designed for high reactive current circulation and must include overcurrent, overvoltage, and fault protection.
With the updated 2.5 nF load and confirmed >=10 A peak output current target, the output stage should be designed for at least 10 A peak capacitive current and should be checked for switching loss, reactive energy recovery, and thermal stress at 500 kHz.
Preliminary Architecture Direction
Recommended architecture for the next design phase:
-
220 VAC input protection and EMI filtering
- Fuse
- MOV/GDT/surge protection
- NTC or active inrush limiting
- Common-mode and differential-mode EMI filtering
-
AC/DC front end
- Rectifier and bulk capacitor
- Optional PFC or regulated high-voltage intermediate bus depending on power and compliance target
-
Isolated high-voltage supply rails
- Target rails likely around +/-1.1 kV to +/-1.5 kV to provide headroom for +/-1000 V output
- Exact rail voltage depends on selected amplifier topology and modulation margin
-
High-voltage output amplifier
- Candidate: multi-level SiC/GaN switching amplifier with high-voltage feedback
- Candidate: cascaded lower-voltage modules summed/stacked to meet voltage and slew-rate targets
- Conventional single-stage linear amplifier is not preferred due to 3140 V/us sine-wave slew-rate, 4000 V/us arbitrary-waveform dv/dt limit, and high reactive current demand
-
Feedback and protection
- High-voltage divider for output feedback
- Current sensing for capacitive-load current and short-circuit protection
- Output slew-rate limiting to enforce =10 A peak current target provides margin for the sinusoidal case, but arbitrary waveform edges must be limited to <=4000 V/us to stay within 10 A peak.
- A practical design may require a multi-level or modular architecture to reduce device voltage stress and switching loss.
- Safety compliance, isolation requirements, enclosure design, and operator protection must be defined before final PCB layout.
- China-made component preference must not override safety, voltage rating, isolation certification, thermal margin, or datasheet availability.
Next Design Steps
- Select system topology: multi-level switching amplifier vs modular stacked amplifier vs hybrid linear/switching architecture.
- Define waveform generator/interface behavior to enforce the <=4000 V/us output dv/dt limit.
- Define safety/compliance targets and isolation requirements.
- Build a detailed power budget and reactive-current budget.
- Select HV supply architecture and power-path protection components, prioritizing China-made / China-supply-chain parts where technically suitable.
- Select output-stage devices and gate drivers from datasheets.
- Create the new schematic in functional blocks.
- Simulate output-stage behavior with the 2.5 nF load before PCB layout.
Purpose
Confirmed User Requirements
Component Sourcing and Manufacturing Preference
Derived Electrical Requirements
Voltage Gain
Capacitive Load Current
Maximum dv/dt Limit
Sine-Wave Slew Rate Check
Output Power and Reactive Energy
Preliminary Architecture Direction
Key Risks / Open Design Decisions
Next Design Steps
