Project Specification — High Voltage Arbitrary Waveform Amplifier
Purpose
Design a new high-voltage wideband power amplifier. This replaces the previous recovered/manufacturing-data-based flyback ultrasonic pulse board concept; the old T1 flyback topology is not suitable for the new arbitrary-waveform target.
Confirmed User Requirements
Table
Parameter
Requirement
AC input supply
220 VAC mains
Signal input
+/-10 V arbitrary waveform
Output voltage
+/-1000 V peak
Load
2.5 nF capacitive load
Frequency range
0 to 500 kHz
Output current capability
>=10 A peak
Maximum output dv/dt
=10 A peak output capability provides margin above the calculated 7.85 A peak sinusoidal capacitive current requirement. Arbitrary waveforms with faster edges can still require higher instantaneous current because i = C*dv/dt, so the output stage must include current limiting and slew-rate-aware protection.
Maximum dv/dt Limit
For a capacitive load, current is directly proportional to voltage slew rate:
Therefore arbitrary output waveforms must be slew-rate limited to =10 A peak output-current target. Faster edges would exceed the output current specification.
Sine-Wave Slew Rate Check
For a sine wave at 500 kHz and 1000 V peak:
SR = 2pif*Vpk
SR = 2pi500 kHz*1000 V = 3.14e9 V/s = 3140 V/us
This is below the 4000 V/us current-limited dv/dt maximum, so a 500 kHz, +/-1000 Vpeak sine wave is compatible with the 2.5 nF, >=10 A peak target. However, non-sinusoidal arbitrary waveforms must be checked against the 4000 V/us dv/dt limit.
Output Power and Reactive Energy
The load is primarily capacitive. The instantaneous current can be high even if average real power depends on load loss and energy recovery. The output stage and supply must be designed for high reactive current circulation and must include overcurrent, overvoltage, and fault protection.
With the updated 2.5 nF load and confirmed >=10 A peak output current target, the output stage should be designed for at least 10 A peak capacitive current and should be checked for switching loss, reactive energy recovery, and thermal stress at 500 kHz.
Preliminary Architecture Direction
Recommended architecture for the next design phase:
220 VAC input protection and EMI filtering
Fuse
MOV/GDT/surge protection
NTC or active inrush limiting
Common-mode and differential-mode EMI filtering
AC/DC front end
Rectifier and bulk capacitor
Optional PFC or regulated high-voltage intermediate bus depending on power and compliance target
Isolated high-voltage supply rails
Target rails likely around +/-1.1 kV to +/-1.5 kV to provide headroom for +/-1000 V output
Exact rail voltage depends on selected amplifier topology and modulation margin
High-voltage output amplifier
Candidate: multi-level SiC/GaN switching amplifier with high-voltage feedback
Candidate: cascaded lower-voltage modules summed/stacked to meet voltage and slew-rate targets
Conventional single-stage linear amplifier is not preferred due to 3140 V/us sine-wave slew-rate, 4000 V/us arbitrary-waveform dv/dt limit, and high reactive current demand
Feedback and protection
High-voltage divider for output feedback
Current sensing for capacitive-load current and short-circuit protection
Output slew-rate limiting to enforce =10 A peak current target provides margin for the sinusoidal case, but arbitrary waveform edges must be limited to <=4000 V/us to stay within 10 A peak.
A practical design may require a multi-level or modular architecture to reduce device voltage stress and switching loss.
Safety compliance, isolation requirements, enclosure design, and operator protection must be defined before final PCB layout.
China-made component preference must not override safety, voltage rating, isolation certification, thermal margin, or datasheet availability.
Next Design Steps
Select system topology: multi-level switching amplifier vs modular stacked amplifier vs hybrid linear/switching architecture.
Define waveform generator/interface behavior to enforce the <=4000 V/us output dv/dt limit.
Define safety/compliance targets and isolation requirements.
Build a detailed power budget and reactive-current budget.
Select HV supply architecture and power-path protection components, prioritizing China-made / China-supply-chain parts where technically suitable.
Select output-stage devices and gate drivers from datasheets.
Create the new schematic in functional blocks.
Simulate output-stage behavior with the 2.5 nF load before PCB layout.