修正PCB短路与浮铜

已按“模块接口”完成输出级原理图骨架,没有放入任何错误的三脚 MOSFET 替代件。
已添加并连接:
  • CELL_DC_P / CELL_DC_N:输出单元直流母线接口
  • CELL_OUT:半桥/多电平单元输出节点
  • HS_GATE / HS_KS:高边未来 CI90N120SM4 的 Gate / Kelvin Source 接口
  • LS_GATE / LS_KS:低边未来 CI90N120SM4 的 Gate / Kelvin Source 接口
  • HS_GATE_DRV / LS_GATE_DRV:栅极驱动输入接口
  • RGH_CELL / RGL_CELL = 2.5Ω:门极串联电阻占位
  • RGH_PD / RGL_PD = 10kΩ:Gate-Kelvin Source 下拉
  • CDCELL_HF = 100nF / 1200V:输出单元高频母线旁路占位
检查结果:原理图接口网络已建立;当前报错主要是 PCB 尚未为新增模块接口放置/布线产生的 airwires,以及已有布局中的一个 overlapping copper。下一步应导入/创建 CI90N120SM4 四引脚器件 后,把这些接口替换为真实 MOSFET 符号并继续完善栅极驱动和保护。
备选方案 Microchip MSC025SMA120B4N怎么样
我会把 Microchip MSC025SMA120B4N 作为非国产备选来评估:重点核对耐压、电流、RDS(on)、Qg、Kelvin 源极、驱动电压和开关损耗,再判断是否适合作为临时原理图器件或最终备选。
Working for 2 days 17 hrs...
Thought for 6 sec
Reading MSC025SMA120B4N datasheet for absolute maximum ratings VDS VGS continu.
Reading MSC025SMA120B4N datasheet for electrical characteristics RDS on gate t.
Reading MSC025SMA120B4N datasheet for switching characteristics turn on energy.
Reading MSC025SMA120B4N datasheet for pin configuration package TO-247-4 Kelvi...
与外界的联系只有供电输入,信号输入输出

Pulling up the datasheet...

ROC_HYS P1 - ROC_PULLUP P2
COC_REF P1 - ROC_REF_BOT P1
CLOAD P2 - J5 P2
R1 P1 - RFB1 P2
J_QL_SK P2 - RGL_PD P2
DVN1 K - T1 SEC_2_2.5V_@1.1A_2
J4 P1 - RG1 P1
J_QH_DG P2 - RGH_CELL P2
BR1 + - CBUS1 P1
COC_REF P1 - ROC_REF_BOT P1
CLOAD P1 - J5 P1
F1 P1 - J1 P1
J_QH_SK P2 - RGH_PD P2
BR1 + - CBUS1 P1
J_CELL_PWR P2 - J_QL_SK P1
CLOAD P2 - J5 P2
CLOAD P1 - J5 P1
CLOAD P1 - J5 P1
T1 SEC_2_2.5V_@1.1A_1 - UOC1 2
J4 P2 - R7 P1
J_QL_DG P2 - RGL_CELL P2
CLOAD P2 - J5 P2
J_CELL_PWR P1 - J_QH_DG P1
BR1 - - CBUS1 P2
CHVN1 P2 - CHVP1 P2
CHVN1 P2 - CHVP1 P2
R3 P2 - RFB5 P1
COC_IN P1 - ROC_HYS P2
T1 SEC_2_2.5V_@1.1A_1 - UOC1 2
CHVN1 P2 - CHVP1 P2
J_GATE_DRV P1 - RGH_CELL P1
CHVP1 P1 - CHV_POS P1
COC_REF P1 - ROC_REF_BOT P1
ROC_HYS P1 - ROC_PULLUP P2
R1 P2 - R2 P1
BR1 AC - CX1 P2
BR1 AC - CX1 P1
BR1 + - CBUS1 P1
COC_DEC P1 - ROC_PULLUP P1
CHVN1 P2 - CHVP1 P2
BR1 + - CBUS1 P1
RFB10 P2 - RFB5 P2
CLOAD P1 - J5 P1
J_CELL_OUT P1 - J_QH_SK P1
R1 P2 - R2 P1
CHVN1 P1 - CHV_NEG P1
COC_IN P1 - ROC_HYS P2
R4 P2 - R5 P1
J_GATE_DRV P1 - RGH_CELL P1
J_CELL_OUT P1 - J_QH_SK P1
R4 P1 - RFB6 P2
R1 P1 - RFB1 P2
F1 P1 - J1 P1
CHVN1 P2 - CHVP1 P2
CHVN1 P2 - CHVP1 P2
R2 P2 - R3 P1
R5 P2 - R6 P1
J_QH_DG P2 - RGH_CELL P2
DVN1 K - T1 SEC_2_2.5V_@1.1A_2
J_GATE_DRV P2 - RGL_CELL P1
CHVN1 P2 - CHVP1 P2
CHVN1 P2 - CHVP1 P2
R4 P2 - R5 P1
CHVN1 P1 - CHV_NEG P1
R5 P2 - R6 P1
R6 P2 - RFB10 P1
CLOAD P2 - J5 P2
J_QL_DG P2 - RGL_CELL P2
DVP1 A - T1 SEC_1_2.5V_@1.1A_1
BR1 - - CBUS1 P2
CHVP1 P1 - CHV_POS P1
CHVP1 P1 - CHV_POS P1
J_CELL_PWR P1 - J_QH_DG P1
COC_IN P1 - ROC_HYS P2
J4 P2 - R7 P1
BR1 AC - CX1 P2
COC_REF P1 - ROC_REF_BOT P1
CHVP1 P1 - CHV_POS P1
CHVP1 P1 - CHV_POS P1
CHVN1 P1 - CHV_NEG P1
CHVP1 P1 - CHV_POS P1
CHVN1 P1 - CHV_NEG P1
CHVN1 P2 - CHVP1 P2
CHVN1 P2 - CHVP1 P2
BR1 AC - CX1 P2
BR1 AC - CX1 P1
CHVN1 P1 - CHV_NEG P1
J_GATE_DRV P2 - RGL_CELL P1
ROC_HYS P1 - ROC_PULLUP P2
R6 P2 - RFB10 P1
J_CELL_PWR P1 - J_QH_DG P1
R4 P1 - RFB6 P2
DVP1 A - T1 SEC_1_2.5V_@1.1A_1
R3 P2 - RFB5 P1
BR1 - - CBUS1 P2
J_QL_SK P2 - RGL_PD P2
BR1 + - CBUS1 P1
J_CELL_PWR P2 - J_QL_SK P1
J_CELL_PWR P2 - J_QL_SK P1
J_QH_SK P2 - RGH_PD P2
COC_DEC P1 - ROC_PULLUP P1
J_QH_DG P2 - RGH_CELL P2
CHVN1 P2 - CHVP1 P2
COC_DEC P1 - ROC_PULLUP P1
CHVN1 P2 - CHVP1 P2
J4 P1 - RG1 P1
CHVN1 P2 - CHVP1 P2
BR1 AC - CX1 P1
RFB10 P2 - RFB5 P2
R2 P2 - R3 P1
BR1 AC - CX1 P1
BR1 AC - CX1 P2
BR1 - - CBUS1 P2
COC_DEC P1 - ROC_PULLUP P1
BR1 + - CBUS1 P1
BR1 - - CBUS1 P2
BR1 AC - CX1 P1
COC_IN P1 - ROC_HYS P2
J_QL_DG P2 - RGL_CELL P2
J_CELL_PWR P2 - J_QL_SK P1
CLOAD P2 - J5 P2
J_CELL_OUT P1 - J_QH_SK P1
CHVN1 P1 - CHV_NEG P1
BR1 AC - CX1 P2
CLOAD P2 - J5 P2
CHVN1 P2 - CHVP1 P2
UOC1
RHVN_DIS
Resistance
10MΩ
RFB6
Resistance
2.49MΩ
R3
Resistance
2.49MΩ
RBUS2
Resistance
330kΩ
RFB1
Resistance
2.49MΩ
ROC_PULLUP
Resistance
4.7kΩ
RHV_IN_NEG
Resistance
10Ω
R7
Resistance
1kΩ
RBUS1
Resistance
330kΩ
RHVP_DIS
Resistance
10MΩ
RHV_IN_POS
Resistance
10Ω
RGH_CELL
Resistance
2.5Ω
RGL_CELL
Resistance
2.5Ω
RHV_BLEED_POS
Resistance
20MΩ
RSH1
Resistance
0.1Ω
ROC_IN
Resistance
100Ω
ROC_REF_TOP
Resistance
15.6kΩ
R1
Resistance
2.49MΩ
ROC_HYS
Resistance
1MΩ
R6
Resistance
2.49MΩ
RCX1
Resistance
1MΩ
RFB5
Resistance
100kΩ
R4
Resistance
2.49MΩ
RG1
Resistance
1kΩ
R5
Resistance
2.49MΩ
ROC_REF_BOT
Resistance
1kΩ
RFB10
Resistance
100kΩ
RHV_BLEED_NEG
Resistance
20MΩ
RGH_PD
Resistance
10kΩ
RGL_PD
Resistance
10kΩ
R2
Resistance
2.49MΩ
T1
J_GATE_DRV
CBUS1
Capacitance
220µF
RV1
BR1
CHV_POS
Capacitance
1nF
J_QL_DG
CX1
Capacitance
100nF
J_CELL_OUT
CBUS2
Capacitance
220µF
CHVN1
Capacitance
4.7nF
CHV_NEG
Capacitance
1nF
J4
CDCELL_HF
Capacitance
100nF
F1
J_QH_DG
J1
CHVP1
Capacitance
4.7nF
J_QL_SK
COC_DEC
Capacitance
100nF
J_CELL_PWR
J5
COC_IN
Capacitance
100pF
CLOAD
Capacitance
1nF
J_QH_SK
COC_REF
Capacitance
10nF
DVP2
DVN2
DVN1
DVP1

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HV Amplifier System Architecture
Confirmed Target
  • Input power: 220 VAC mains
  • Signal input: +/-10 V arbitrary waveform
  • Output: +/-1000 V peak
  • Load: 2.5 nF capacitive
  • Frequency: 0 to 500 kHz
  • Output current: >=10 A peak
  • Slew-rate limit: 1.5 kV with adequate creepage and power dissipation
  • Output current sensor/shunt/CT suitable for >=10 A peak and 500 kHz
  • Overvoltage clamp and discharge/bleeder
  • HV output connector and load connector
Open Design Decisions
  • Number of cascaded output cells and per-cell DC bus voltage
  • Whether waveform fidelity requires linear post-correction or pure high-rate PWM/multilevel synthesis is acceptable
  • Required distortion/accuracy/settling error specification
  • Isolation and safety compliance target
  • Cooling method and maximum continuous operating duty cycle
Immediate Next Step
Search for candidate components, prioritizing China-made / China-supply-chain parts:
  • 650 V or 1200 V SiC/GaN/MOSFET power devices
  • isolated gate drivers
  • isolated DC/DC supplies
  • HV divider resistors/capacitors
  • mains protection and rectification parts
  • controller/ADC/DAC/FPGA or high-speed MCU parts
  • Confirmed Target

  • Key Electrical Consequences

  • Selected Preliminary Topology

  • Functional Blocks for Schematic

  • Block A — Mains Input and Protection

  • Block B — Control Power

  • Block C — Controller / Waveform Interface

  • Block D — Isolated Gate Drive

  • Block E — HV Output Power Stage

  • Block F — Output Measurement and Protection

  • Open Design Decisions

  • Immediate Next Step

HV Arbitrary Waveform Amplifier thumbnail
220VAC-powered high-voltage arbitrary waveform amplifier targeting ±1000Vpeak into 2.5nF, 0–500kHz, ≥10A peak with ≤4000V/µs slew-rate limit; component selection prioritizes China-made / China-supply-chain parts where safe and technically suitable.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$1.10–$2.50

Digi-Key

$1.02

HQonline

$0.30

LCSC

$1.95–$2.17

Mouser

$8.88–$10.22

TME

$2.23

Verical

$1.70–$4.32

Controls