修正PCB短路与浮铜
CELL_DC_P / CELL_DC_N:输出单元直流母线接口CELL_OUT:半桥/多电平单元输出节点HS_GATE / HS_KS:高边未来 CI90N120SM4 的 Gate / Kelvin Source 接口LS_GATE / LS_KS:低边未来 CI90N120SM4 的 Gate / Kelvin Source 接口HS_GATE_DRV / LS_GATE_DRV:栅极驱动输入接口RGH_CELL / RGL_CELL = 2.5Ω:门极串联电阻占位RGH_PD / RGL_PD = 10kΩ:Gate-Kelvin Source 下拉CDCELL_HF = 100nF / 1200V:输出单元高频母线旁路占位Pulling up the datasheet...
Confirmed Target
Key Electrical Consequences
Selected Preliminary Topology
Functional Blocks for Schematic
Block A — Mains Input and Protection
Block B — Control Power
Block C — Controller / Waveform Interface
Block D — Isolated Gate Drive
Block E — HV Output Power Stage
Block F — Output Measurement and Protection
Open Design Decisions
Immediate Next Step