GND Copper Fill Setup
Worked for 1 min 48 sec
Findings, read-only:
- Live DRC shows 28 GND-related airwire errors, not ~65 in the current check.
- The polygon is electrically assigned to the same effective net as GND pads: GND effectiveNetId =
ace6b8eb..., and the polygon also has that same effective net. - The airwire labels like
GND_1,GND_5,SHELL_GND, etc. are mostly pad names/designators, not separate schematic nets. The schematic summary shows only one main GND net plus the intentional separate DMX_ISO_GND net. - Several GND pads inspected are on the same GND net and use Direct connect thermal behavior by default. Lack of an explicit “Thermal Relief” rule is therefore not the main reason the polygon fails to clear airwires, though you may still want relief-connect for solderability.
- The most likely issue is that the polygon is present and net-bound, but the airwire checker is not seeing it as baked/merged routed copper to the pads — i.e. a fill recompute/refresh or generated-fill connectivity issue, not a schematic net-name issue.
- One thing to double-check visually: the polygon path I read appears to include a left/top lobe near the DMX area; confirm it truly does not cross the isolation region.
Recommended next check: force a copper pour recompute/refresh in the PCB editor, then re-run Airwires DRC. If GND still reports 28, the polygon may need pad thermal/keepout rules adjusted or converted into generated fill geometry that the DRC recognizes as routed copper.
Force a copper fill / polygon recompute in the PCB editor, then re-run the Airwires DRC. Report the new airwire count.
Thought for 7 sec
I’ll try to trigger a copper-fill refresh/recompute using the available PCB operations, then re-run the Airwires check and report the updated count.
Worked for 1 min 23 sec
I could not find an exposed API operation that explicitly forces a copper-pour recompute in the PCB editor, so I re-ran the live Airwires DRC check after the attempted refresh path.
Results:
- Total Airwires DRC errors: 77
- GND-related airwires: still 28
- Review timestamp: 2026-06-19T21:23:16Z
So the GND polygon still is not being counted as routed/merged copper for those GND pads.
Diagnose GND airwires
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Power Stage Design Notes
Requirements
- Input: 12V DC nominal from off-board panel XLR-4 connector, brought onto PCB at J2 screw terminal.
- Input range: 11V to 16.8V.
- Protection order: J2 -> 5A slow-blow fuse holder F1 -> P-channel MOSFET reverse polarity protection Q1 -> bidirectional TVS D2.
- Protected input feeds a 5A buck pre-regulator set to about 12.5V.
- 12V_REG bus feeds future motor connectors and the 3V3 buck.
- 3V3 buck powers ESP32-S3 and future logic, rated at least 1A.
Current Budget Used for Sizing
Table
| Rail | Load | Design Current |
|---|---|---|
| 12V_REG | Two Dynamixel X-series servos with firmware current limit | 2A each, 4A total target |
| 12V_REG | Margin for wiring, slip ring, and logic buck input | 1A |
| 3V3 | ESP32-S3 + future logic allowance | 1A requested, 2A regulator selected |
| 3V3 | NEO-M8N GPS receiver | 67mA max from datasheet example |
| 3V3 | Active GPS antenna bias from VCC_RF | up to 50mA available from module VCC_RF |
| 3V3 | DS3231 RTC + I2C pull-ups | <5mA active, µA backup |
Reflected 3V3 load into 12V_REG assuming 90% buck efficiency:
- 3V3 at 1A: about 0.31A from 12V_REG.
- 3V3 at 2A regulator limit: about 0.61A from 12V_REG.
- GPS/RTC additions remain well within the existing 3V3 regulator margin.
The input protection chain is therefore tagged for 5A continuous design current, matching the motor-bus cap/current target. With the added Dynamixel connectors, the nominal design assumes two motors limited in firmware to about 2A each plus 1A margin. If firmware current limits are raised or stall/inrush current must be supported continuously, the input fuse, MOSFET thermal design, terminal block current rating, JST-EH connector rating, 12V regulator, and trace widths must be revisited.
Dynamixel Connector Power Notes
- J5 and J6 are JST-EH 3-pin motor connectors.
- JST EH datasheet current rating: 3A per contact with AWG #22 wire.
- Pinout: pin 1 GND, pin 2 12V_REG, pin 3 DXL_DATA.
- The 12V_REG rail remains annotated as 5A max for PCB layout trace sizing.
GPS / RTC Power Notes
- GPS U6 is powered from 3V3; datasheet maximum example supply current is 67mA at about 3V.
- U6 VCC_RF can source active antenna bias current up to 50mA; it feeds the U.FL antenna line through L3 RF choke.
- RTC U7 VBAT backup is a 0.22F supercapacitor. R15=1k limits initial charge current from 3V3 to about 3.3mA before diode drop, so it is negligible versus the 2A 3V3 regulator rating.
Selected Topology and Parts
- J2: XY301V-A-5.0-2P 2-position screw terminal, 15A-class input connector.
- F1: Littelfuse 178.7017.0001 PCB fuse holder for user-installed 5A slow-blow fuse.
- Q1: DMP3017SFG-7 P-channel MOSFET; -30V VDS, ±25V VGS, low RDS(on), used as reverse-polarity ideal-diode element.
- D2: SMBJ18CA-13-F bidirectional TVS; VRWM 18V, VBR 20.0V to 23.3V, VC 29.2V at rated pulse current.
- U2: TPS5450DDAR 5A adjustable buck; input range 5.5V to 36V, 500kHz.
- U3: AP63203WU-7 fixed 3.3V, 2A synchronous buck; input range 3.8V to 32V.
12.5V Pre-Regulator Details
TPS5450 feedback uses VREF = 1.221V. With R6 = 92.4k and R7 = 10k:
VOUT = 1.221 * (1 + 92.4k / 10k) = about 12.5V.
TPS5450 support passives added:
- C4: 10uF input capacitor.
- C5: 100nF high-frequency input bypass.
- C6: 10nF bootstrap capacitor from BOOT to PH.
- L1: 6.8uH inductor, 8A current rating target.
- D3: SS56 Schottky catch diode from PH to GND.
- C7: 330uF low-ESR output bulk capacitor.
- C8: 100nF output bypass.
3V3 Buck Details
AP63203 datasheet recommended fixed-3.3V application:
- L2: 3.9uH inductor.
- C9: 10uF input capacitor.
- C10: 100nF bootstrap capacitor from BST to SW.
- C11/C12: 2x22uF output capacitors.
- EN tied to 12V_REG for automatic startup.
- FB tied to 3V3 output for fixed-output sensing.
Layout Notes for Later
- Keep Q1, D2, U2, L1, D3, and C4/C5/C7 tightly grouped with short high-current loops.
- Route 12V_IN_RAW, 12V_FUSED, 12V_PROTECTED, and 12V_REG as high-current nets sized for 5A with thermal margin.
- Keep U2 PH/SW copper compact and away from ESP32 antenna/USB pair.
- Place U3 close to the ESP32 3V3 consumers, but keep its SW node compact and away from USB D+/D-.
Requirements
Current Budget Used for Sizing
Dynamixel Connector Power Notes
GPS / RTC Power Notes
Selected Topology and Parts
12.5V Pre-Regulator Details
3V3 Buck Details
Layout Notes for Later
