GND Copper Fill Setup

flux

Findings, read-only:
  • Live DRC shows 28 GND-related airwire errors, not ~65 in the current check.
  • The polygon is electrically assigned to the same effective net as GND pads: GND effectiveNetId = ace6b8eb..., and the polygon also has that same effective net.
  • The airwire labels like GND_1, GND_5, SHELL_GND, etc. are mostly pad names/designators, not separate schematic nets. The schematic summary shows only one main GND net plus the intentional separate DMX_ISO_GND net.
  • Several GND pads inspected are on the same GND net and use Direct connect thermal behavior by default. Lack of an explicit “Thermal Relief” rule is therefore not the main reason the polygon fails to clear airwires, though you may still want relief-connect for solderability.
  • The most likely issue is that the polygon is present and net-bound, but the airwire checker is not seeing it as baked/merged routed copper to the pads — i.e. a fill recompute/refresh or generated-fill connectivity issue, not a schematic net-name issue.
  • One thing to double-check visually: the polygon path I read appears to include a left/top lobe near the DMX area; confirm it truly does not cross the isolation region.
Recommended next check: force a copper pour recompute/refresh in the PCB editor, then re-run Airwires DRC. If GND still reports 28, the polygon may need pad thermal/keepout rules adjusted or converted into generated fill geometry that the DRC recognizes as routed copper.
N

narush

Force a copper fill / polygon recompute in the PCB editor, then re-run the Airwires DRC. Report the new airwire count.

flux

I’ll try to trigger a copper-fill refresh/recompute using the available PCB operations, then re-run the Airwires check and report the updated count.

flux

I could not find an exposed API operation that explicitly forces a copper-pour recompute in the PCB editor, so I re-ran the live Airwires DRC check after the attempted refresh path.
Results:
  • Total Airwires DRC errors: 77
  • GND-related airwires: still 28
  • Review timestamp: 2026-06-19T21:23:16Z
So the GND polygon still is not being counted as routed/merged copper for those GND pads.
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Schematic

Layout

3D View

Routing Preflight Blockers
U2 TPS5450DDAR Footprint
Requested fix: clone the current U2 footprint into a project-local custom footprint, delete four non-electrical mount pads, preserve the single GND exposed PowerPAD, and reassign U2.
Observed tool limitation: no existing project-local TPS5450 footprint asset was available, and the available asset tool can import assets from external URLs but cannot extract/edit/re-save the embedded footprint asset. As a layout-level mitigation, the four embedded non-electrical mount pads were set to 0.0 mm x 0.0 mm and 0.0 mm keepout. The real U2 EP pad remains active, rectangular, 2.29 mm x 2.29 mm, directly connected to GND with solder mask expansion 0.05 mm and paste expansion 0.0 mm.
12V Neckdown Requirement
Requested rule: 12V bulk routing stays 1.5 mm, with short tapered transitions up to 3 mm length down to pad width at SMD/connector pads.
The board currently has 1.5 mm minimum width set on 12V_IN_RAW, 12V_FUSED, 12V_PROTECTED, and 12V_REG. Router preflight previously flagged the following narrow-pad conflicts:
  • C5 P1 on 12V_PROTECTED
  • C8 P1 on 12V_REG
  • C9 P1 on 12V_REG
  • Q1 S pins on 12V_PROTECTED
  • U2 VIN on 12V_PROTECTED
  • U3 EN on 12V_REG
  • U3 VIN on 12V_REG
Proposed/required resolution: add explicit fanout/neckdown geometry at these pads: 1.5 mm bulk trace or pour transitioning to pad width over <=3 mm. If generated neckdown polygons are not available, manually route these short entries as tapered copper regions before running the general router.
Pins Inside Keepouts
Preflight reported these pins inside keepouts. Most are support passives located close to IC pins or inside component courtyard/keepout envelopes; the preferred fix is a local keepout relaxation around the pin/pad, not group reorganization.

Table

PinProposed local fix
C10 P1Slight local keepout relaxation around C10 pads or shift C10 <=0.5 mm away from its IC while preserving decoupling proximity.
C10 P2Same as C10 P1.
C13 P1Local keepout relaxation or <=0.5 mm passive shift.
C1 P1Local keepout relaxation; keep near ESP32 power pin.
C28 P1Local keepout relaxation or <=0.5 mm shift near RTC/supercap network.
C3 P1Local keepout relaxation; keep near ESP32 reset/boot support.
C8 P1Local keepout relaxation plus 12V neckdown at pad.
C9 P1Local keepout relaxation plus 12V neckdown at pad.
D6 ALocal keepout relaxation or <=0.5 mm shift in RTC supercap charge path.
D6 KSame as D6 A.
F1 pin 2Local keepout relaxation around high-current fuse pad; do not reduce isolation gap.
R10 P1Local keepout relaxation or small passive shift.
R10 P2Same as R10 P1.
R13 P1Local keepout relaxation near I2C pull-up.
R13 P2Same as R13 P1.
R15 P1Local keepout relaxation or small shift near RTC backup charge path.
R15 P2Same as R15 P1.
R1 P1Local keepout relaxation near ESP32 EN network.
R1 P2Same as R1 P1.
R6 P1Local keepout relaxation plus 12V_REG neckdown if needed.
R8 P1Local keepout relaxation near DMX termination switch network; preserve isolation side.
R8 P2Same as R8 P1.
SW2 switch pinLocal keepout relaxation around DMX termination switch; preserve isolated-side-only copper.
U2 PHLocal keepout relaxation around U2 pad; keep switching loop compact.
U2 VINLocal keepout relaxation plus 12V_PROTECTED neckdown.
U3 BSTLocal keepout relaxation around U3 bootstrap pin.
U3 ENLocal keepout relaxation plus 12V_REG neckdown if required by net assignment.
U3 FBLocal keepout relaxation; preserve feedback divider proximity.
U3 SWLocal keepout relaxation; keep switching copper area small.
U3 VINLocal keepout relaxation plus 12V_REG neckdown.
Constraints for all fixes:
  • Do not alter the DMX isolation gap.
  • Do not connect GND and DMX_ISO_GND.
  • Do not place copper under the ESP32 WROOM antenna keepout.
  • Keep RF traces away from U2/U3 switching nodes.

  • U2 TPS5450DDAR Footprint

  • 12V Neckdown Requirement

  • Pins Inside Keepouts