GND Copper Fill Setup
Worked for 1 min 48 sec
Findings, read-only:
- Live DRC shows 28 GND-related airwire errors, not ~65 in the current check.
- The polygon is electrically assigned to the same effective net as GND pads: GND effectiveNetId =
ace6b8eb..., and the polygon also has that same effective net. - The airwire labels like
GND_1,GND_5,SHELL_GND, etc. are mostly pad names/designators, not separate schematic nets. The schematic summary shows only one main GND net plus the intentional separate DMX_ISO_GND net. - Several GND pads inspected are on the same GND net and use Direct connect thermal behavior by default. Lack of an explicit “Thermal Relief” rule is therefore not the main reason the polygon fails to clear airwires, though you may still want relief-connect for solderability.
- The most likely issue is that the polygon is present and net-bound, but the airwire checker is not seeing it as baked/merged routed copper to the pads — i.e. a fill recompute/refresh or generated-fill connectivity issue, not a schematic net-name issue.
- One thing to double-check visually: the polygon path I read appears to include a left/top lobe near the DMX area; confirm it truly does not cross the isolation region.
Recommended next check: force a copper pour recompute/refresh in the PCB editor, then re-run Airwires DRC. If GND still reports 28, the polygon may need pad thermal/keepout rules adjusted or converted into generated fill geometry that the DRC recognizes as routed copper.
Force a copper fill / polygon recompute in the PCB editor, then re-run the Airwires DRC. Report the new airwire count.
Thought for 7 sec
I’ll try to trigger a copper-fill refresh/recompute using the available PCB operations, then re-run the Airwires check and report the updated count.
Worked for 1 min 23 sec
I could not find an exposed API operation that explicitly forces a copper-pour recompute in the PCB editor, so I re-ran the live Airwires DRC check after the attempted refresh path.
Results:
- Total Airwires DRC errors: 77
- GND-related airwires: still 28
- Review timestamp: 2026-06-19T21:23:16Z
So the GND polygon still is not being counted as routed/merged copper for those GND pads.
Diagnose GND airwires
Inspect commit diff
Explain recompute workflow
Create repair plan
Check manufacturability
Refine this doc
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Project Specification — DMX Solar Pan-Tilt Mirror Controller
Purpose
Controller PCB for a DMX-controlled motorized pan/tilt mirror head using two Dynamixel servos and GPS-based solar tracking.
Current Build Step: MCU Block
- Main controller: ESP32-S3-WROOM-1-N16R8 module (U1), 16 MB flash + 8 MB PSRAM.
- Power: module powered from external 3V3 rail; regulator to be added in a later step.
- Decoupling: C1 100 nF and C2 10 uF on 3V3 near U1.
- Reset/enable: EN net has R1 10 kΩ pull-up to 3V3 and C3 100 nF to GND.
- Boot: GPIO0 has R2 10 kΩ pull-up to 3V3 and SW1 momentary button to GND.
- USB: ESP32-S3 native USB uses GPIO19 = USB_D_N and GPIO20 = USB_D_P to USB-C connector J1.
- USB-C configuration: R4/R5 5.1 kΩ CC pull-downs for USB device/sink behavior.
- Status LED: GPIO2 drives D1 through R3 1 kΩ, LED cathode to GND.
MCU Block Sourcing Notes
- Generic passives now include initial manufacturer/MPN metadata for assembly review:
- R1/R2: 10 kΩ 0603 pull-ups, VO 0603 ±1% 10K, LCSC C2889366.
- R4/R5: 5.1 kΩ 0603 USB-C CC pull-downs, Vishay CRCW06035K10JNEAC.
- R3: 1 kΩ 0603 LED resistor, Vishay CRCW06031K00JNEAC.
- C1/C3: 100 nF 0603 ceramic, Samsung CL10B104KB8NNNC, LCSC C1591.
- C2: 10 uF 0603 ceramic, Yageo CC0603KRX5R6BB106.
Validation Status
- Schematic MCU block connectivity is complete for this step.
- Remaining review errors after this step are expected layout-stage items only: PCB airwires/overlap because placement and routing have not started yet.
GPIO Constraints
- Do not use GPIO26–GPIO37 for application I/O; GPIO35–GPIO37 are connected to Octal SPI PSRAM on this N16R8 module.
- Strapping pins accounted for: GPIO0 is BOOT-controlled; GPIO3, GPIO45, and GPIO46 are left unused for now.
- Native USB pins GPIO19/GPIO20 are reserved for USB flashing/debug.
Next Planned Blocks
- Final schematic review/cleanup, then board setup and placement after confirmation.
Power Stage Added
- Input connector: J2 accepts 11V to 16.8V nominal 12V DC from the off-board XLR-4/panel wiring.
- Protection chain: J2 -> F1 5A slow-blow fuse holder -> Q1 DMP3017SFG-7 P-channel MOSFET reverse-polarity stage -> D2 SMBJ18CA bidirectional TVS.
- 12V pre-regulator: U2 TPS5450DDAR buck regulator set to about 12.5V on 12V_REG using R6=92.4k and R7=10k.
- 3V3 regulator: U3 AP63203WU-7 fixed 3.3V/2A buck from 12V_REG, feeding the existing 3V3 rail for U1 and logic.
- Detailed calculations, selected passives, and layout constraints are recorded in the Power Stage Design Notes project file.
Isolated DMX-512 Receive Stage Added
- Isolated transceiver: U4 ADM2587EBRWZ with integrated isolated DC/DC.
- Logic side: U4 VCC pins connect to 3V3; U4 GND1 pins connect to main GND; U4 RxD connects to ESP32 GPIO4 on DMX_RX.
- Direction control: U4 ~RE and DE are tied together on DMX_REDE and routed to ESP32 GPIO5; R9 pulls this net low so default state is receive-enabled / driver-disabled.
- TxD idle bias: R10 pulls U4 TxD high so the unused transmit input does not float.
- Line side: U4 A/B connect to DMX_A/DMX_B; J3 is DMX IN and J4 is DMX THRU, wired in parallel using XLR-5 mapping pin 1 common/shield, pin 2 Data-, pin 3 Data+, pins 4/5 unused.
- Termination: R8 120 ohm termination is switchable across DMX_A/DMX_B via SW2 for end-of-chain use.
- Protection: D4 TVS array protects DMX_A/DMX_B to DMX_ISO_GND.
- Isolation rule: DMX_ISO_GND is the only line-side ground and is intentionally not connected to main GND. Keep the ADM2587E isolation barrier clear in PCB layout.
Dynamixel Half-Duplex Servo Bus Added
- Logic interface: U5 SN74LVC2G241DCTR dual tri-state buffer powered from 3V3 with C21 100 nF local decoupling.
- ESP32 pin map: GPIO17 = DXL_TX into U5 1A; GPIO18 = DXL_RX from U5 2Y; GPIO16 = DXL_DIR driving U5 1~OE and 2OE together.
- Direction behavior: DXL_DIR LOW enables TX buffer from ESP32 to DATA; DXL_DIR HIGH disables TX and enables DATA-to-RX buffer. R12 10 kΩ pulls DXL_DIR high so the bus defaults to receive/listen during reset.
- Shared DATA line: U5 1Y drives DXL_DATA through R11 27 Ω series damping resistor; DXL_DATA returns through U5 2A/2Y to ESP32 RX.
- Protection: D5 PESD3V3L5UY low-capacitance ESD/TVS array protects DXL_DATA to main GND.
- Motor connectors: J5 = local pan motor, J6 = slip-ring/off-board tilt motor. Both are JST-EH 3-pin vertical headers compatible with Dynamixel X-series Robot Cable-X3P.
- Connector pinout: pin 1 = GND, pin 2 = 12V_REG, pin 3 = DXL_DATA.
- Current note: JST-EH is rated about 3 A/contact; firmware target current limit is about 2 A per motor, so the connector rating is acceptable for the intended continuous limit. The 12V_REG rail remains sized at 5 A for two limited motors plus logic overhead.
GPS and RTC Solar Tracking Block Added
- GPS: U6 u-blox NEO-M8N powered from 3V3, with local 100 nF and 10 uF decoupling.
- GPS UART: U6 TXD connects to ESP32 RXD0/GPIO44 on GPS_TX_TO_ESP_RX; U6 RXD connects to ESP32 TXD0/GPIO43 on GPS_RX_FROM_ESP_TX.
- GPS backup: U6 V_BCKP is tied to 3V3 with local C25 decoupling for valid backup-domain bias while the controller is powered.
- Active antenna: U6 RF_IN is AC-coupled through C26 to GPS_RF_ANT; U6 VCC_RF biases the active antenna line through L3 RF choke; J7 U.FL connects to the external active GPS antenna via U.FL-to-panel-SMA pigtail.
- RF layout constraint: GPS_RF_IN/GPS_RF_ANT must be routed as a short 50 ohm controlled-impedance RF path, kept away from U2/U3 switching nodes and inductors.
- RTC: U7 DS3231 on I2C bus with SDA=GPIO8 and SCL=GPIO9; R13/R14 are 4.7 kΩ pull-ups to 3V3.
- RTC backup: U7 VBAT is held by C22 0.22F supercapacitor with C28 local decoupling; it charges from 3V3 through R15 1 kΩ and D6 Schottky diode. No coin cell is used.
Purpose
Current Build Step: MCU Block
MCU Block Sourcing Notes
Validation Status
GPIO Constraints
Next Planned Blocks
Power Stage Added
Isolated DMX-512 Receive Stage Added
Dynamixel Half-Duplex Servo Bus Added
GPS and RTC Solar Tracking Block Added
