Layout Setup Notes
Board Outline
- Shape: rectangular.
- Size: 90 mm x 68 mm.
- Edge margin / board inset: 0.5 mm.
- No placement or routing performed in this setup step.
Stackup
Configured as a custom Standard 4 Layer stackup, 1 oz copper on all copper layers:
- Top Copper: signal, components, RF.
- Mid-Layer 1: solid ground plane, reference for RF, USB, and high-speed signals.
- Mid-Layer 2: power plane for 12V_REG and 3V3 regions.
- Bottom Copper: signal routing and secondary decoupling.
Current stackup dielectric used for impedance estimates:
- Top copper to Layer 2 ground reference: approximately 0.26 mm FR-4 prepreg.
- Relative dielectric constant used for estimates: about 4.3.
- Copper thickness: 0.035 mm.
Global Rules
- Default trace width: 0.2 mm.
- Default minimum trace width: 0.2 mm.
- Default clearance / keepout: 0.2 mm.
- Board edge margin: 0.5 mm.
- Preferred trace widths added: 0.2 mm, 0.6 mm, 1.5 mm, 2.5 mm.
- Via target for routing stage: 0.3 mm drill / 0.6 mm pad, tented on outer layers where possible. No vias exist yet, so this will be enforced during routing setup.
Net Classes / Constraints
POWER_12V
Nets: 12V_IN_RAW, 12V_FUSED, 12V_PROTECTED, 12V_REG.
- Target current: up to 5 A.
- Constraint applied: trace width/min trace width 2.5 mm.
- Preferred implementation: copper pour/polygon on Layer 3 and/or wide top/bottom copper.
- J5/J6 motor pin 2 paths require at least 1.5 mm; the 12V_REG net rule of 2.5 mm exceeds this.
POWER_3V3
Net: 3V3.
- Constraint applied: trace width/min trace width 0.6 mm.
RF
Nets: GPS_RF_ANT, GPS_RF_IN.
- Controlled impedance: 50 ohm single-ended, referenced to Layer 2 ground plane.
- Computed starting trace width: approximately 0.45 mm.
- Constraint applied: trace width/min trace width 0.45 mm.
- Keep RF short and away from U2/U3 switching regulators and inductors.
USB
Nets: USB_D_P, USB_D_N.
- Controlled impedance: 90 ohm differential pair, referenced to Layer 2 ground plane.
- Computed starting geometry: 0.35 mm trace width with about 0.225 mm pair gap.
- Constraint applied to each USB net: trace width/min trace width 0.35 mm.
- Pair must be routed length-matched during routing.
SIGNAL
Everything else.
- Uses default trace width/clearance: 0.2 mm.
Notes
- Impedance values are first-pass closed-form estimates based on the configured stackup. Final production impedance should be verified against the PCB fabricator field solver / impedance calculator.
- Components are currently not placed within the board outline; placement is intentionally deferred per the request.
DMX Isolation Partition
- Isolated DMX domain: nets DMX_ISO_GND, DMX_VISO, DMX_A, DMX_B and components U4 field side, D4, J3, J4, C17, C18, C19, C20.
- These isolated components were grouped into a dedicated top-left board-edge island.
- U4 is the only component that may bridge the isolation boundary.
- A visible dashed marker named DMX Isolation Gap Marker was added at the U4 barrier location. Treat this as a no-copper keepout on every copper layer: no fills, traces, or vias across this corridor.
- A visible marker named DMX_ISO_GND Island Marker outlines the isolated ground island area. Layer 2 must be split so the main GND plane excludes this island and DMX_ISO_GND fills only this isolated region.
- GND and DMX_ISO_GND must remain separate copper regions on every layer. No stitching capacitors, jumpers, vias, or copper pours may connect them unless the schematic is explicitly changed.
- Target creepage across the isolation gap: at least 8 mm.