Migration Reconstruction and Safety Review

flux

Completed the 12 V KVM branch verification/reconstruction only: VIN_PROTECTED → MOD3 → 12V_RAW → F4 → +12V → J4, with MOD3 EN tied to VIN, PG intentionally NC, LED3/R11 on 12V_RAW, TP6 on +12V, and J4 mapped as A=+12V center, B=GND sleeve, C intentionally NC. No PCB layout work was done.
Open items:
  • F4 holder is 6.3 A rated, but the fuse element remains documented as provisional 1 A; this conflicts with the 12 V 2 A requirement until fuse/load/inrush validation is done.
  • No dedicated 12V_RAW test point was found; TP6 is the fused +12V test point.
  • MOD3 footprint evidence is limited to the documented Pololu module/interface and D36V28Fx-FS; no unverified pin/footprint assumptions were added.
  • Label intent KVM 12V / B1 is preserved in documents, but no separate silkscreen object was verified.
  • No MOD3/J4 ERC issues were returned; the project still has the known non-KVM MOD1:VCC false-positive ERC and the 43-vs-44 net accounting gap.
Suggested next steps:
  1. Reconstruct/verify the USB-C PD charge-input and interlock block next.
  2. Reconcile the missing 44th net.
  3. Run full ERC after all schematic blocks are restored.
mansingh33

mansingh33

flux

I can’t run auto-layout right now because AI execution is unavailable: the account has no available ACUs. I’m not able to call the placement/routing tools until ACUs are available again.
What has been completed so far:
  • Recreated and verified the main schematic documentation set.
  • Reconstructed/verified these phase 3 schematic blocks:
    • Protected 5S battery input/protection block.
    • Raspberry Pi 5.1 V branch.
    • LCD 5.0 V branch.
    • 12 V KVM branch.
  • Preserved intentional no-connects and warnings, including MOD1 VCC as the known TPSM63606 ERC false positive.
  • No PCB layout work has been started or validated.
What remains before auto-layout is appropriate:
  • Finish schematic reconstruction for the USB-C PD charge/interlock subsystem and any remaining blocks.
  • Reconcile the expected 44 nets vs current 43 nets.
  • Run full ERC and resolve/document all remaining issues.
  • Then proceed to PCB placement first, followed by routing. Current state likely needs both placement and routing, but final layout should wait until schematic/ERC reconciliation is complete.
Find net mismatch
Finish USB-C subsystem
List remaining blocks
Review BOM issues
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Migration Phase 3 Schematic Reconstruction Report
Date: 2026-07-24
Scope: Schematic reconstruction only. PCB layout was not started.
Result Summary
A schematic was reconstructed from the parsed native .flx evidence, BOM/source bundle, engineering package, and recreated project files. The implementation preserves the major architecture and verified safety constraints:
  • protected 5S LiPo input path,
  • LTC4365 protection/interlock architecture,
  • back-to-back MOSFET protection stage,
  • fused 5.1 V, 5 V, and 12 V outputs,
  • J2/J3 source-only USB-C output roles,
  • J5 charge-only/sink-only USB-C role,
  • generic MOD4/MOD5/MOD6 charger interfaces with release blockers,
  • F1–F5 serviceable fuse holders,
  • J6 NTC connector and J7 charge-current jumper,
  • TP1–TP14 test points,
  • intentionally unconnected TPSM63606 VCC pin,
  • balance-harness prohibition and BMS gates.
Current Schematic/BOM Counts

Table

ItemCurrent reconstructed targetSource/evidence expectationStatus
BOM-bearing component instances74Source reported 116 visible schematic componentsPartial; major functional BOM restored, exact parity not reached
Total schematic objects including portals/grounds/NC328Parsed .flx stored elements: 341Close but not exact 1:1 visual/object parity
Nets43Parsed .flx reports 44 nets43 functional nets restored; one expected .flx net remains unaccounted/discrepant
PCB layout workNot performedSource has 680 layout nodes/465 route vertices/0 routesNot started; not fabrication-ready
Major Restored Components
Restored verified / evidence-backed designators include:
  • J1, F1, SW1, U1, Q1, Q2, D1, C1–C23, R1–R16, LED1–LED3.
  • MOD1 TPSM63606RDLR, MOD2 Pololu D36V28F5, MOD3 Pololu D36V28F12.
  • J2/J3 USB4235-03-C source-only output connectors.
  • J4 Tensility 54-00127 KVM barrel jack.
  • J5 USB4235-03-C charge-only/sink-only input connector.
  • MOD4 1×8 TBD PD sink interface, MOD5 1×12 TBD charger interface, MOD6 1×4 TBD reverse blocker interface.
  • F2–F5 Littelfuse 64900001039 serviceable fuse holders.
  • J6/J7 Molex 1722861102 connectors.
  • U2 VO615A-3X017T optocoupler and D3 TPD2E2U06DCKR CC ESD protection.
  • TP1–TP14 Keystone 5002 test points.
Functional Nets Restored
The reconstructed schematic currently has 43 named nets:
  • BAT_PROTECTED
  • BAT_FUSED
  • VIN_SW
  • VIN_PROTECTED
  • GND
  • GATE_DRIVE
  • MOSFET_COMMON_SOURCE
  • PROTECTION_IN
  • SHDN_PULLUP
  • LTC_DIV_MID_HIGH
  • LTC_OV
  • LTC_UV
  • 5V1_RAW
  • +5V1
  • J2_CC1_RP
  • J2_CC2_RP
  • 5V0_RAW
  • +5V0
  • J3_CC1_RP
  • J3_CC2_RP
  • 12V_RAW
  • +12V
  • LED1_ANODE
  • LED2_ANODE
  • LED3_ANODE
  • USB_CHG_VBUS_RAW
  • USB_CHG_CC1
  • USB_CHG_CC2
  • PD_20V
  • PD_20V_OK
  • CHARGER_EN_REQ
  • CHARGER_OUT
  • CHARGE_BLOCKED
  • PACK_NTC
  • PACK_NTC_RETURN
  • CHARGE_ISET_1A
  • CHARGE_2A_ENABLE
  • CHARGE_STATUS
  • FULL_STATUS
  • FAULT_STATUS
  • CHARGE_INTERLOCK_LED
  • MOD1_PGOOD
  • MOD1_RBOOT_CBOOT_SHORT
  • MOD1_FB
The parsed .flx states 44 expected nets. The available extracted 44-net table was partial and included several auto-label style names. Therefore one net remains a documented discrepancy until the complete parsed net list can be compared pin-by-pin.
ERC Status
Fresh ERC readiness check reports one remaining electrical error:

Table

CheckClassificationAction
Power input not connected: MOD1:VCCKnown false positive / library pin-type defectPreserved intentionally. TI defines VCC as an internal LDO output; do not connect external loads or tie it to a rail to silence ERC.
All floating-pin ERC errors from the reconstruction pass were cleared. Multiple schematic-legibility warnings may exist because this phase did not recreate exact visual wire geometry/placement.
Explicit Discrepancies / Blockers
  • Exact 1:1 component count is not achieved: 74 BOM instances / 328 total schematic objects vs source reports of 116 visible components / 341 stored elements.
  • Net count is 43 vs the parsed .flx expectation of 44; the missing net remains explicitly unaccounted.
  • R13 remains unresolved: source history conflicts between 360 Ω / 2 W, 3.3 kΩ / 0.25 W, and 1.5 kΩ / 0.5 W. It is marked R13_VALUE_CONFLICT and must be verified against the authoritative parsed component property before release.
  • MOD4/MOD5/MOD6 are intentionally generic/TBD interfaces. Exact modules, pinouts, footprints, logic polarity/levels, NTC behavior, reverse leakage, and charger configuration remain release blockers.
  • MOD5 was recreated with a library 1×12 header to represent the saved TBD charger interface, not an approved charger module footprint.
  • J1 XT60 was restored from a verified library candidate because the exact original J1 part UID was not exposed in the source chunks read during this phase.
  • Balance harness remains unmapped. No cell-tap assignments were created.
  • No PCB layout, routing, DRC, current-density, thermal, mechanical, charging, backfeed, or battery-safety validation has been performed.
Readiness for ERC / Next Step
The schematic is ready for a focused ERC review pass with one expected known false-positive (MOD1:VCC) and documented reconstruction discrepancies. It is not ready for PCB layout until the user accepts these discrepancies or provides complete parsed .flx component/net evidence for exact parity.

  • Result Summary

  • Current Schematic/BOM Counts

  • Major Restored Components

  • Functional Nets Restored

  • ERC Status

  • Explicit Discrepancies / Blockers

  • Readiness for ERC / Next Step