Migration Reconstruction and Safety Review
Start Auto-Layout
Thought for 7 sec
I can’t run auto-layout right now because AI execution is unavailable: the account has no available ACUs. I’m not able to call the placement/routing tools until ACUs are available again.
What has been completed so far:
- Recreated and verified the main schematic documentation set.
- Reconstructed/verified these phase 3 schematic blocks:
- Protected 5S battery input/protection block.
- Raspberry Pi 5.1 V branch.
- LCD 5.0 V branch.
- 12 V KVM branch.
- Preserved intentional no-connects and warnings, including MOD1
VCCas the known TPSM63606 ERC false positive. - No PCB layout work has been started or validated.
What remains before auto-layout is appropriate:
- Finish schematic reconstruction for the USB-C PD charge/interlock subsystem and any remaining blocks.
- Reconcile the expected 44 nets vs current 43 nets.
- Run full ERC and resolve/document all remaining issues.
- Then proceed to PCB placement first, followed by routing. Current state likely needs both placement and routing, but final layout should wait until schematic/ERC reconciliation is complete.
Find net mismatch
Finish USB-C subsystem
List remaining blocks
Review BOM issues
Refine this doc
Ask about this doc
Connector Pinout Table
Date restored: 2026-07-24
Status: Evidence-derived / verify during schematic reconstruction
Status: Evidence-derived / verify during schematic reconstruction
Critical Warning
Do not infer any balance-wire assignments from photographs, seller diagrams, connector colors, or 3D/layout exports. The balance harness remains unmapped unless measured and documented.
J1 — Battery / Off-Board BMS Input
Role: input from off-board 5S common-port BMS P+/P−.
Table
| Pin / Contact | Net | Notes |
|---|---|---|
| Pos | BAT_PROTECTED | Off-board BMS P+; also connects to F1 input, F5 charge injection, TP1 |
| Neg | GND | Off-board BMS P− / system ground |
No raw cell taps or balance harness connections are authorized on J1.
SW1 — Off-Board Master Switch Loop
Resolved interface: TE Connectivity 282837-2 terminal block. Actual off-board switch must be maintained SPST, accessible, and rated ≥5 A at ≥30 VDC.
Table
| Pin | Net | Notes |
|---|---|---|
| 1 | BAT_FUSED / switch out | From F1 output |
| 2 | VIN_SW / switch return | Feeds protected input path |
J2 — Raspberry Pi 400 USB-C Source Output
Role: 5.1 V source-only output; passive Rp; no USB-PD; no data.
Table
| Contact group | Net / role | Notes |
|---|---|---|
| VBUS A4/A9/B4/B9 | +5V1 | Fused Pi 5.1 V output |
| GND and shield contacts | GND | Common ground |
| CC1 / CC2 | Source Rp network | Advertise source current; no sink behavior |
| D+/D−/SBU | NC | Intentionally no data/SBU |
Functional label:
PI 5.1V OUT.J3 — LCD USB-C Source Output
Part evidence: USB4235-03-C_REVA. Role Details evidence: LCD source-only USB-C; passive 3 A Rp; no USB-PD and no data.
Table
| Contact group | Net / role | Notes |
|---|---|---|
| VBUS A4/A9/B4/B9 | +5V0 | Fused LCD 5 V output |
| GND and shield contacts | GND | Common ground |
| CC1 / CC2 | Source Rp network | Source-only advertisement |
| D+/D−/SBU | NC | Intentionally no data/SBU |
Functional label:
LCD 5V OUT.J4 — KVM Barrel Output
Resolved part: Tensility 54-00127, 5.5 × 2.1 mm right-angle THT, 48 V / 6 A. Center-positive.
Table
| Pin | Net | Notes |
|---|---|---|
| A | +12V | Center pin / KVM positive |
| B | GND | Sleeve |
| C | NC | Switched sleeve contact intentionally unconnected |
Functional label:
KVM 12V. Verify actual KVM plug before manufacturing.J5 — USB-C Charge Input
Part evidence: USB4235-03-C_REVA. Role: CHARGE ONLY — SINK ONLY — NO SOURCE/OTG — NO Rp.
Table
| Contact group | Net | Notes |
|---|---|---|
| VBUS A4/A9/B4/B9 | USB_CHG_VBUS_RAW | Raw charge VBUS input |
| CC1 | USB_CHG_CC1 | To MOD4 protected PD sink module |
| CC2 | USB_CHG_CC2 | To MOD4 protected PD sink module |
| GND and shield contacts | GND | Common ground |
| D+/D−/SBU | NC | Intentionally no data/SBU |
Supporting charge-input components from source evidence:
- D3 TPD2E2U06DCKR: IO1 → CC1, IO2 → CC2, GND →
GND. - D2 SMBJ24CA-class provisional TVS:
USB_CHG_VBUS_RAWtoGND, final coordination required. - C15: 100 nF from
USB_CHG_VBUS_RAWtoGND. - C16: DNI/TBD bulk footprint from
USB_CHG_VBUS_RAWtoGND. - TP7:
USB_CHG_VBUS_RAW.
MOD4 — USB-C PD Sink Module Interface
Generic 1×8 connector. Exact module, connector, footprint, logic polarity/levels, and mechanical details are release blockers.
Table
| Pin | Net | Intended function |
|---|---|---|
| 1 | USB_CHG_VBUS_RAW | VBUS input |
| 2 | GND | Return |
| 3 | USB_CHG_CC1 | CC1 |
| 4 | USB_CHG_CC2 | CC2 |
| 5 | PD_20V | Negotiated/gated 20 V output |
| 6 | PD_20V_OK | PD-good status |
| 7 | NC / module enable if required | Not connected in saved mapping; exact module may differ |
| 8 | GND | Return |
TP8 →
PD_20V; TP9 → PD_20V_OK.MOD5 — 5S Charger Module Interface
Generic 1×12, 2.54 mm header. Intended module: genuine preassembled 5S buck-boost CC/CV charger, 21.0 V maximum. Exact module/pinout/footprint/logic remain release blockers.
Table
| Pin | Net | Intended function |
|---|---|---|
| 1 | PD_20V | VIN+ |
| 2 | GND | VIN− |
| 3 | CHARGER_OUT | BAT+ / charger output |
| 4 | GND | BAT− |
| 5 | CHARGER_EN_REQ | Charger enable request |
| 6 | PACK_NTC | NTC input |
| 7 | PACK_NTC_RETURN | NTC return |
| 8 | CHARGE_ISET_1A | 1 A setting node |
| 9 | CHARGE_2A_ENABLE | 2 A enable request |
| 10 | CHARGE_STATUS | Charge status |
| 11 | FULL_STATUS | Full status |
| 12 | FAULT_STATUS | Fault status |
Support:
- C17: 100 nF from
PD_20VtoGND. - C18: DNI/TBD bulk from
PD_20VtoGND. - C19: 100 nF from
CHARGER_OUTtoGND. - C20: DNI/TBD bulk from
CHARGER_OUTtoGND. - TP10 →
CHARGER_OUT. - TP11 →
CHARGE_STATUS. - TP12 →
FULL_STATUS. - TP13 →
FAULT_STATUS.
MOD6 — Reverse-Current Blocker Interface
TBD ≥30 V / ≥3 A ideal-diode or reverse-current-blocking module. Required unless selected charger proves reverse blocking.
Table
| Pin | Net | Intended function |
|---|---|---|
| 1 | CHARGER_OUT | Input from charger |
| 2 | GND | Return |
| 3 | CHARGE_BLOCKED | Reverse-blocked output |
| 4 | GND | Return |
F5 — Charge Fuse
Table
| Pin | Net | Notes |
|---|---|---|
| 1 | CHARGE_BLOCKED | From MOD6 output |
| 2 | BAT_PROTECTED | Injection to protected battery node |
Evidence includes a provisional 2.5 A charge fuse. Final rating/time-current/interrupt behavior remains charger-dependent.
Charge Enable and Interlock Nodes
Table
| Part / node | Connection | Notes |
|---|---|---|
| R15 pin 1 | PD_20V_OK | DNI/TBD |
| R15 pin 2 | CHARGER_EN_REQ | Populate only after logic verification |
| R14 pin 1 | CHARGER_EN_REQ | 10 kΩ pull-down path |
| R14 pin 2 | GND | Safe-off default |
| U2 LED anode path | USB_CHG_VBUS_RAW → R13 → CHARGE_INTERLOCK_LED | Value conflict in source; verify final schematic evidence |
| U2 LED cathode | GND | Charge-present detector |
| U2 collector | SHDN_PULLUP | Pulls U1 #SHDN low when active |
| U2 emitter | GND | Return |
| R4 | VIN_SW to SHDN_PULLUP | 100 kΩ pull-up evidence |
J6 — Pack NTC Connector
Part evidence: Molex 1722861102, 2-position.
Table
| Pin | Net | Notes |
|---|---|---|
| 1 | PACK_NTC | External 10 kΩ NTC physically attached to LiPo pack |
| 2 | PACK_NTC_RETURN | NTC return |
J6 is not a balance connector. Missing/out-of-range NTC must inhibit charging.
J7 — Charge-Current Configuration Jumper
Part evidence: Molex 1722861102, normally open.
Table
| Pin | Net | Notes |
|---|---|---|
| 1 | CHARGE_ISET_1A | Default-open intent: 1 A |
| 2 | CHARGE_2A_ENABLE | Closing requests 2 A only after approval |
J7 is not a balance connector. Exact charger setting logic remains a release blocker.
Test Point Summary
Table
| Test point | Net / role |
|---|---|
| TP1 | BAT_PROTECTED |
| TP7 | USB_CHG_VBUS_RAW |
| TP8 | PD_20V |
| TP9 | PD_20V_OK |
| TP10 | CHARGER_OUT |
| TP11 | CHARGE_STATUS |
| TP12 | FULL_STATUS |
| TP13 | FAULT_STATUS |
| TP14 | TPSM63606 PGOOD evidence |
| Other required TPs | VIN_SW, VIN_PROTECTED, raw/fused output rails, GND |
Source Gaps
The source evidence did not expose a complete final connector table for every original component. This file preserves the explicit mappings recovered from the migration bundle and parsed
.flx excerpts. During schematic reconstruction, every connector and pin must be checked against the full parsed .flx net list and BOM evidence.Critical Warning
J1 — Battery / Off-Board BMS Input
SW1 — Off-Board Master Switch Loop
J2 — Raspberry Pi 400 USB-C Source Output
J3 — LCD USB-C Source Output
J4 — KVM Barrel Output
J5 — USB-C Charge Input
MOD4 — USB-C PD Sink Module Interface
MOD5 — 5S Charger Module Interface
MOD6 — Reverse-Current Blocker Interface
F5 — Charge Fuse
Charge Enable and Interlock Nodes
J6 — Pack NTC Connector
J7 — Charge-Current Configuration Jumper
Test Point Summary
Source Gaps
