Migration Reconstruction and Safety Review

mansingh33

mansingh33

flux

I can’t run auto-layout right now because AI execution is unavailable: the account has no available ACUs. I’m not able to call the placement/routing tools until ACUs are available again.
What has been completed so far:
  • Recreated and verified the main schematic documentation set.
  • Reconstructed/verified these phase 3 schematic blocks:
    • Protected 5S battery input/protection block.
    • Raspberry Pi 5.1 V branch.
    • LCD 5.0 V branch.
    • 12 V KVM branch.
  • Preserved intentional no-connects and warnings, including MOD1 VCC as the known TPSM63606 ERC false positive.
  • No PCB layout work has been started or validated.
What remains before auto-layout is appropriate:
  • Finish schematic reconstruction for the USB-C PD charge/interlock subsystem and any remaining blocks.
  • Reconcile the expected 44 nets vs current 43 nets.
  • Run full ERC and resolve/document all remaining issues.
  • Then proceed to PCB placement first, followed by routing. Current state likely needs both placement and routing, but final layout should wait until schematic/ERC reconciliation is complete.
Find net mismatch
Finish USB-C subsystem
List remaining blocks
Review BOM issues

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Ask about this doc
Board Bring-Up Plan
Date restored: 2026-07-24
Status: Draft validation plan / not fabrication-ready
Safety Preconditions
  • Do not connect the real LiPo battery for initial bring-up.
  • Do not connect or probe an unverified balance harness.
  • Use current-limited bench supplies, dummy loads, a proper 5S battery simulator, or five isolated cell simulators where applicable.
  • Perform first real-pack tests in a fire-safe setup with a bench fuse and supervision.
  • Do not approve based on “not too hot to touch”; record temperatures and compare against datasheet limits plus margin.
Phase 0 — Documentation and Assembly Review
  1. Confirm Project Specification, Design Notes - Power and Safety, Connector Pinout Table, PCB Assembly Notes, and this Bring-Up Plan are current.
  2. Confirm all release blockers are still visible.
  3. Confirm the board is not claimed fabrication-ready unless schematic, layout, DRC, thermal, mechanical, charging, backfeed, and battery-safety validation are complete.
  4. Confirm J2/J3 are source-only USB-C outputs and J5 is charge-only/sink-only.
  5. Confirm J6 is pack NTC only and J7 is charge-current configuration only.
  6. Confirm no balance harness connector or cell-tap mapping has been added.
Phase 1 — Unpowered Inspection
  1. Inspect assembly, polarity, unpopulated options, solder bridges, MOSFET orientation, fuse holders, USB-C soldering, barrel jack pins, and switch-loop wiring.
  2. Confirm source-output USB-C connectors J2/J3 are not confused with charge input J5.
  3. Confirm J5 labeling says charge-only / sink-only / no source or OTG.
  4. Confirm R15 remains DNI/TBD until PD_20V_OK level/polarity is verified.
  5. Confirm optional 2 A charge setting remains disabled/open unless explicitly approved.
  6. Confirm charger modules/jumpers remain absent or disabled during output-path bring-up unless the current step explicitly tests them.
Phase 2 — Continuity and Isolation, No Battery
With all power removed:
  1. Check for shorts from every rail to GND: BAT_PROTECTED, BAT_FUSED, VIN_SW, VIN_PROTECTED, 5V1_RAW, +5V1, 5V0_RAW, +5V0, 12V_RAW, +12V, USB_CHG_VBUS_RAW, PD_20V, CHARGER_OUT, and CHARGE_BLOCKED.
  2. Verify fuse input/output separation for F1–F5.
  3. Verify F5, MOD6, and charge-path isolation.
  4. Verify J4 center-positive mapping before connecting any KVM device.
  5. Verify J6 NTC connector is isolated from any unverified balance harness.
  6. Verify USB data and SBU pins on J2/J3/J5 are intentionally not used.
Phase 3 — Protected Input Path Bring-Up
  1. Use current-limited bench supply instead of real battery.
  2. Apply low voltage first, then step through expected operating range.
  3. Verify LTC4365 UV falling threshold near 16.50 V typical.
  4. Verify reconnect near 17.33 V typical.
  5. Verify OV rising near 23.57 V typical and reset near 22.39 V typical.
  6. Verify back-to-back MOSFET behavior and no unexpected heating.
  7. Verify VIN_PROTECTED only appears when U1 enables the path.
  8. Verify charge-present U2 interlock can shut down the load path when J5 VBUS is present.
Phase 4 — Output Rail Bring-Up
Bring up each output rail independently with dummy loads first.
5.1 V Pi Rail
  1. Verify TPSM63606 input and support components.
  2. Confirm TPSM63606 VCC remains intentionally unconnected externally.
  3. Verify 5.100 V nominal output.
  4. Test PGOOD / TP14 behavior if present.
  5. Step load to intended Pi current envelope.
  6. Verify F2 element behavior is suitable for load and inrush before approval.
5 V LCD Rail
  1. Verify Pololu D36V28F5 input/output mapping.
  2. Verify 5.0 V output.
  3. Step load toward intended LCD current.
  4. Verify F3 element behavior and inrush.
12 V KVM Rail
  1. Verify Pololu D36V28F12 input/output mapping.
  2. Verify 12 V output.
  3. Verify J4 center-positive polarity.
  4. Step load toward intended KVM current.
  5. Verify F4 element behavior and inrush.
Phase 5 — USB-C Source Output Tests
For J2/J3 only:
  1. Verify passive Rp values on CC1/CC2.
  2. Verify no USB-PD claim is made on source-output connectors.
  3. Verify no USB data/SBU connections.
  4. Test attach/detach behavior.
  5. Verify VBUS discharge/current-limit behavior if implemented by the chosen source circuit.
  6. Verify short-circuit response with current-limited equipment.
Phase 6 — Staged USB-C PD Charger Bring-Up
Do not use the real battery until all charger stages pass with safe equipment.
Stage 6.1 — Charge Path Continuity and Isolation
  • Verify J5 → USB_CHG_VBUS_RAW → MOD4 → PD_20V → MOD5 → CHARGER_OUT → MOD6 → CHARGE_BLOCKED → F5 → BAT_PROTECTED continuity only where expected.
  • Verify no backfeed path from BAT_PROTECTED to J5 VBUS.
  • Verify F5 is the only intended injection path into BAT_PROTECTED.
Stage 6.2 — 5 V / No-Contract Behavior
  • Connect a 5 V-only USB-C source.
  • Verify charger does not enable.
  • Verify PD_20V_OK is not asserted.
  • Verify U2 load-shutdown interlock still disables the system outputs when raw VBUS is present.
Stage 6.3 — 20 V PD Negotiation
  • Connect a current-limited PD source capable of ordinary 20 V / ≥3 A.
  • Verify 20 V contract on PD_20V.
  • Verify PD_20V_OK polarity and logic level.
  • Do not populate/enable R15 until this behavior is confirmed.
Stage 6.4 — Charger Enable Safe-Off
  • Confirm R14 holds CHARGER_EN_REQ safe-off by default.
  • Populate/enable the PD-good link only after logic-level verification.
  • Verify failed PD negotiation cannot enable charging.
Stage 6.5 — NTC Fault Matrix
Use resistor substitution on J6:
  • Normal 10 kΩ at 25 °C equivalent: charging permitted.
  • Open NTC: charging inhibited.
  • Shorted NTC: charging inhibited.
  • Cold equivalent: charging inhibited.
  • Hot equivalent: charging inhibited.
Stage 6.6 — Dummy-Battery CC/CV Test
  • Use a 5S battery simulator or electronic load setup, not the real pack.
  • Verify precharge behavior if applicable.
  • Verify 21.00 V maximum CC/CV regulation.
  • Verify default 1 A current limit.
  • Verify termination behavior and safety timer.
Stage 6.7 — Optional 2 A Test
  • Only perform if pack, BMS, charger, fuse, copper, connector, and thermal limits are already approved.
  • Close J7 only under controlled test conditions.
  • Verify actual requested current and thermal behavior.
  • Reopen J7 afterward unless 2 A is approved for production.
Stage 6.8 — Status Outputs
Verify test points:
  • TP11 / CHARGE_STATUS.
  • TP12 / FULL_STATUS.
  • TP13 / FAULT_STATUS.
Stage 6.9 — Reverse-Blocking and Backfeed
  • Verify battery simulator cannot drive current backward into MOD5/MOD4/J5 VBUS when USB is absent.
  • Verify reverse leakage is within selected module/device limits.
  • Verify MOD6 or charger reverse-blocking behavior in powered and unpowered states.
Stage 6.10 — SW1-OFF and Load Shutdown Tests
  • Verify load outputs stay disabled while charge VBUS is present.
  • Verify charger behavior with SW1 off and on.
  • Verify no unexpected load powering/backfeed paths.
Stage 6.11 — Gated Real-Battery Test
Only after all prior stages pass:
  1. Use verified real pack through bench fuse and fire-safe setup.
  2. Confirm BMS common-port charging support and charge-current rating.
  3. Confirm NTC is physically attached to the LiPo pack.
  4. Start at 1 A default only.
  5. Record voltage, current, temperature, and status transitions.
Phase 7 — Thermal and Full-Load Tests
  1. Run a 60-minute full-load thermal soak in intended enclosure or equivalent thermal fixture.
  2. Test with fan operating and fan blocked.
  3. Record all component and connector temperatures.
  4. Use datasheet limits plus appropriate design margin.
  5. Repeat for charge mode and load mode separately.
  6. Do not approve based on touch temperature.
Phase 8 — Battery/BMS Validation Gates
For any integrated or external BMS validation:
  1. Use cell simulators first.
  2. Verify B0–B5 readings at IC pins if an integrated BMS exists in a future revision.
  3. Verify 4.20 V OV trip and recovery on every channel.
  4. Verify 2.90 V UV trip and 3.30 V recovery.
  5. Verify open-wire behavior.
  6. Verify 0 °C/45 °C charge and −10 °C/65 °C discharge thresholds.
  7. Verify OCD/OCC and short-circuit behavior.
  8. Do not rely on photographs or seller diagrams for cell order.
Pass Criteria Before Fabrication or Use
The design cannot be treated as ready until:
  • Schematic reconstruction matches evidence or discrepancies are documented.
  • ERC issues are resolved or documented as false positives with evidence.
  • Board layout is complete and reviewed.
  • DRC is complete with no unexplained errors.
  • High-current paths pass voltage-drop/current-density review.
  • Thermal tests pass under load and charge conditions.
  • Charger behavior is validated at 5 V/no-contract, 20 V PD, fault, NTC, backfeed, and real-pack stages.
  • BMS common-port charge support is verified.
  • Balance harness remains unmapped unless measured and approved.
  • No fabrication-ready claim is made prematurely.

  • Safety Preconditions

  • Phase 0 — Documentation and Assembly Review

  • Phase 1 — Unpowered Inspection

  • Phase 2 — Continuity and Isolation, No Battery

  • Phase 3 — Protected Input Path Bring-Up

  • Phase 4 — Output Rail Bring-Up

  • 5.1 V Pi Rail

  • 5 V LCD Rail

  • 12 V KVM Rail

  • Phase 5 — USB-C Source Output Tests

  • Phase 6 — Staged USB-C PD Charger Bring-Up

  • Stage 6.1 — Charge Path Continuity and Isolation

  • Stage 6.2 — 5 V / No-Contract Behavior

  • Stage 6.3 — 20 V PD Negotiation

  • Stage 6.4 — Charger Enable Safe-Off

  • Stage 6.5 — NTC Fault Matrix

  • Stage 6.6 — Dummy-Battery CC/CV Test

  • Stage 6.7 — Optional 2 A Test

  • Stage 6.8 — Status Outputs

  • Stage 6.9 — Reverse-Blocking and Backfeed

  • Stage 6.10 — SW1-OFF and Load Shutdown Tests

  • Stage 6.11 — Gated Real-Battery Test

  • Phase 7 — Thermal and Full-Load Tests

  • Phase 8 — Battery/BMS Validation Gates

  • Pass Criteria Before Fabrication or Use

Protected Module-Based 5S Power Distribution Board thumbnail
Carrier PCB for a removable 5S 18.5 V 4000 mAh LiPo-powered Raspberry Pi 400 workstation. Provides protected input, independent low-voltage cutoff, dedicated fused 5.1 V USB-C Pi output, 5 V USB-C LCD output, 12 V center-positive KVM output, cooling-fan power, and a safety-interlocked USB-C PD 5S charging path. This project remains under engineering review and is not fabrication-ready.

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