Migration Reconstruction and Safety Review
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I can’t run auto-layout right now because AI execution is unavailable: the account has no available ACUs. I’m not able to call the placement/routing tools until ACUs are available again.
What has been completed so far:
- Recreated and verified the main schematic documentation set.
- Reconstructed/verified these phase 3 schematic blocks:
- Protected 5S battery input/protection block.
- Raspberry Pi 5.1 V branch.
- LCD 5.0 V branch.
- 12 V KVM branch.
- Preserved intentional no-connects and warnings, including MOD1
VCCas the known TPSM63606 ERC false positive. - No PCB layout work has been started or validated.
What remains before auto-layout is appropriate:
- Finish schematic reconstruction for the USB-C PD charge/interlock subsystem and any remaining blocks.
- Reconcile the expected 44 nets vs current 43 nets.
- Run full ERC and resolve/document all remaining issues.
- Then proceed to PCB placement first, followed by routing. Current state likely needs both placement and routing, but final layout should wait until schematic/ERC reconciliation is complete.
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Finish USB-C subsystem
List remaining blocks
Review BOM issues
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Design Notes - Power and Safety
Date restored: 2026-07-24
Status: Engineering review / not fabrication-ready
Status: Engineering review / not fabrication-ready
Purpose
This file preserves power and safety decisions from the migration evidence. It is not a substitute for schematic reconstruction, ERC, DRC, current-density analysis, thermal testing, charging validation, or battery-safety certification.
Battery and System Safety Context
- Battery: external removable 5S LiPo, 18.5 V nominal, 21.0 V maximum, 4000 mAh, 20C, approximately 74 Wh.
- Main battery connection: XT60 heavy leads through an off-board common-port BMS P+/P−.
- Separate six-wire balance harness: do not connect or map in this carrier revision.
- The six thin wires are cell-voltage taps, not digital communication lines.
- The photographed/seller BMS is unbranded and undocumented; do not reverse-engineer it into the PCB.
Output and Charging Power Budgets
Evidence records separate load and charge expectations:
Table
| Budget | Evidence value | Status |
|---|---|---|
| Output/load budget | 37.3 W prior output-load budget | Must be rechecked after schematic/BOM reconstruction |
| Default charging | 21 W nominal class, 21.0 V at 1 A | Intended default only after charger/BMS validation |
| Optional charging | 42 W nominal class, 21.0 V at 2 A | Disabled/DNI until pack, BMS, fuse, and thermal approval |
Protected Input Implementation
- Controller: LTC4365ITS8-1#TRPBF, TSOT-23-8.
- MOSFETs: 2× PSMN2R0-40YLBX, 40 V, 2.1 mΩ max, common-source back-to-back.
- Divider evidence: 9.6 MΩ / 90 kΩ / 210 kΩ.
- UV falling: 16.50 V typical.
- UV reconnect: 17.33 V typical.
- OV rising: 23.57 V typical.
- OV reset: approximately 22.39 V typical.
- U1
FAULTintentionally unused.
Output Rail Decisions
- MOD1: TI TPSM63606RDLR 5.1 V rail implementation.
- 5.100 V nominal from RFBT 41.0 kΩ and RFBB 10.0 kΩ.
- RRT 13.0 kΩ for 1 MHz reference point.
- CFF 22 pF.
- Input: 2× 10 µF, 50 V, X7R, 1210.
- Output: 2× 47 µF, 10 V, X7R, 1210.
- PGOOD: 100 kΩ pull-up with TP14.
- RBOOT–CBOOT shorted, VLDOIN connected to output, EN/SYNC connected to VIN.
- TI thermal pad, via array, copper plane, capacitor symmetry, and SW-node requirements must be followed in layout.
- MOD2: Pololu D36V28F5, item 3782, 5 V / 3.2 A, 5.3–50 V input.
- MOD3: Pololu D36V28F12, item 3786, 12 V / 2.4 A, 12.9–50 V input.
- D1: Diodes Inc. SMBJ22CA-13-F evidence selection, bidirectional 22 V VRWM, 24.4–28.0 V breakdown, 35.5 V max clamp at 16.9 A. Clamp margin to TPSM63606 36 V limit remains a surge-validation gate.
TPSM63606 VCC ERC False Positive
Evidence records a remaining non-real ERC issue:
Power input not connected: MOD1:VCC.- TI documentation identifies VCC as an internal LDO output with internal capacitor and not an external supply input.
- Do not tie VCC to a rail to silence ERC.
- This must remain documented as a Flux library pin-type/checker issue unless the authoritative current TI datasheet says otherwise.
Fusing and Switching
- F1: main input fuse, intended near 5 A, final element and DC interrupt rating must be verified.
- F2: 3.15 A time-lag provisional Pi branch fuse.
- F3: 2 A provisional LCD branch fuse.
- F4: 1 A provisional KVM branch fuse.
- F5: 2.5 A provisional charge-path fuse.
- Serviceable fuse holder decision: Littelfuse 64900001039 5×20 mm PCB holders, 6.3 A / 250 V holder rating; each fuse element still requires suitable DC interrupt rating and time-current validation.
- SW1 resolved as TE Connectivity 282837-2 terminal interface for off-board maintained SPST switch. The actual off-board switch must be accessible and rated ≥5 A at ≥30 VDC.
Do not accept provisional fuse values automatically. Recalculate from actual continuous current, wire gauge, connector rating, module rating, fault current, fuse location, and measured load inrush.
USB-C Role Safety
- J2/J3: source-only outputs, passive 3 A Rp, no USB-PD and no data.
- J5: charge-only / sink-only input, no source/OTG, no Rp.
- J5 D+/D−/SBU must remain intentionally no-connect unless a future verified design explicitly changes this.
- A 5 V-only source or failed PD negotiation must not enable the charger.
USB-C PD Charging Design Notes
Saved charge path:
J5 → USB_CHG_VBUS_RAW → MOD4 → PD_20V → MOD5 → CHARGER_OUT → MOD6 → CHARGE_BLOCKED → F5 → BAT_PROTECTED- MOD4: protected sink-only USB-PD 3.0 trigger/controller; exact module, connector, footprint, PD-good polarity/level, and no-OTG behavior remain release blockers.
- MOD5: genuine preassembled 5S buck-boost CC/CV charger; exact module, connector, footprint, charge algorithm, safety timer, NTC behavior, status levels, and 21.0 V/1 A settings remain release blockers.
- MOD6: reverse-current blocker required unless MOD5 is independently proven to block battery backfeed in all powered/unpowered states.
- R14: 10 kΩ pull-down to GND for safe-off charger enable default.
- R15: DNI/TBD between
PD_20V_OKandCHARGER_EN_REQpending polarity/level verification. - J6: external 10 kΩ pack NTC connector; open, short, hot, and cold conditions must inhibit charging.
- J7: normally open charge-current jumper; default 1 A; closed 2 A only after BMS/pack/thermal approval.
Charge-Present Load Shutdown
The saved intent is that raw J5 VBUS presence drives U2 optocoupler and pulls LTC4365
#SHDN low through SHDN_PULLUP, disabling the protected load path. This detects USB VBUS presence, not successful PD negotiation.Source evidence contains conflicting R13 values over the revision history:
Table
| Evidence point | R13 value | Notes |
|---|---|---|
| Read-only audit | 360 Ω, 5%, 2 W, 0603 | Older saved mapping text |
| Completed correction | 3.3 kΩ, 5%, 0805, 0.25 W | Calculation showed 5 V/no-contract VBUS can force shutdown |
| Later safety correction | 1.5 kΩ, 5%, 0.5 W, 2512 | Later evidence says this was updated and resistor-power review passed |
Migration rule: preserve the interlock topology, but verify the final intended R13 value against the parsed
.flx component property and current schematic evidence during schematic reconstruction. Do not silently choose a value from conflicting text evidence.BMS and Balance Harness Safety
- Interface only with P+/P− of a proven external 5S common-port BMS for first revision.
- No BMS balance-harness connector or cell-tap mapping is authorized in this carrier PCB.
- J6 is only the pack NTC connector and must not be treated as a balance connector.
- J7 is only the charge-current jumper and must not be treated as a balance connector.
- Do not map cells by wire color. Visible colors in photos are not proof.
- Verify cumulative voltages by multimeter before any future balance connection: approximately 0, 3.7, 7.4, 11.1, 14.8, and 18.5 V for a nominal 5S pack.
Mandatory Assembly and Commissioning Checks
Before any real battery use:
- Verify exact MOD4/MOD5/MOD6 identities, pinouts, footprints, and logic levels.
- Verify MOD4 20 V / ≥3 A PD contract and
PD_20V_OKbehavior; failed negotiation must not enable charging. - Verify MOD5 21.00 V CC/CV regulation, precharge, termination, safety timer, and input-current limiting.
- Verify NTC open/short/hot/cold inhibit behavior.
- Verify J7 default-open is 1 A and optional 2 A is disabled/DNI until approved.
- Verify F5 rating/time-current curve and charge-path thermal performance.
- Verify BMS common-port charging authorization and current rating.
- Verify J5 charge-only labeling and no source/OTG behavior.
- Verify no battery backfeed into USB VBUS.
- Verify system loads are disabled while charge VBUS is present.
Visual and Export Evidence Warning
Photographs, seller diagrams, layer drawings, 3D models, DXF/SVG/PDF exports, STEP/BREP/GLB/VRML/XAO files, and stored layout geometry do not prove balance-pin order, placement completion, routing completion, thermal validity, mechanical clearance, ERC/DRC closure, charging safety, backfeed protection, or fabrication readiness.
Real-World Release Blockers
- Select and validate exact MOD4 PD sink module.
- Select and validate exact MOD5 5S charger module.
- Select MOD6 or prove MOD5 reverse blocking.
- Define final module connectors, footprints, mounting, and bulk values C16/C18/C20 from datasheets.
- Coordinate D1/D2 TVS clamp behavior with all downstream absolute maximum ratings.
- Validate F1–F5 fuse curves, DC interrupt ratings, and thermal behavior.
- Authoritatively verify BMS common-port charging support and charge-current limits.
- Preserve unmapped balance harness until independently verified.
- Complete schematic ERC after reconstruction.
- Complete PCB layout, DRC, current-density, voltage-drop, thermal, mechanical, charging, backfeed, and battery-safety validation before any fabrication claim.
Purpose
Battery and System Safety Context
Output and Charging Power Budgets
Protected Input Implementation
Output Rail Decisions
TPSM63606 VCC ERC False Positive
Fusing and Switching
USB-C Role Safety
USB-C PD Charging Design Notes
Charge-Present Load Shutdown
BMS and Balance Harness Safety
Mandatory Assembly and Commissioning Checks
Visual and Export Evidence Warning
Real-World Release Blockers
