• Accept protected battery power from an external 5S LiPo/BMS P+/P− output.
• Protect the load path against undervoltage and overvoltage using the LTC4365-based cutoff/protection subsystem.
• Provide three separately fused output branches:
  • 5.1 V USB-C source-only output for Raspberry Pi 400.
  • 5.0 V USB-C source-only output for LCD controller.
  • 12 V center-positive barrel output for KVM.
• Provide fan power with clear polarity and appropriate capacity reservation.
• Provide sink-only USB-C PD charging path into BAT_PROTECTED through a verified charger, reverse blocker, and charge fuse.
• Disable system output rails whenever charge VBUS is present through the U2 optocoupler interlock.
• Preserve test points, status outputs, serviceable fuses, safety warnings, and commissioning gates.

• External XT60/BMS P+/P− battery input.
• Main input fuse and off-board master switch interface.
• LTC4365ITS8-1#TRPBF protection controller.
• Back-to-back N-channel MOSFET protection stage.
• TI TPSM63606RDLR 5.1 V output regulator implementation.
• Pololu D36V28F5 5 V module branch.
• Pololu D36V28F12 12 V module branch.
• Two source-only USB-C output receptacles using passive Rp and no USB-PD/data.
• One charge-only/sink-only USB-C receptacle for the charging subsystem.
• External pack NTC connector.
• Charge-current configuration jumper, default 1 A, optional 2 A only after pack/BMS approval.
• Serviceable fuse holders for branch and charge fuses.
• Test points for battery, input, raw/fused rails, charger, status, and ground.

Diagram

• Battery: 5S LiPo, 18.5 V nominal, 21.0 V maximum, 4000 mAh, 20C, approximately 74 Wh.
• Input is from an off-board common-port BMS P+/P−, not raw cell taps.
• LTC4365 thresholds recorded in evidence:
  • UV falling: 16.50 V typical.
  • UV reconnect: 17.33 V typical.
  • OV rising: 23.57 V typical.
  • OV reset: approximately 22.39 V typical.
• Controller: LTC4365ITS8-1#TRPBF.
• MOSFETs: 2× PSMN2R0-40YLBX in common-source back-to-back arrangement.
• U1 FAULT intentionally unused; all other controller pins must be accounted for.

• 5.1 V Pi rail: TI TPSM63606RDLR configured for 5.100 V nominal using documented feedback and support components.
• 5 V LCD rail: Pololu D36V28F5, item 3782.
• 12 V KVM rail: Pololu D36V28F12, item 3786.
• Output path intent:
  • 5V1_RAW → F2 → +5V1 → J2
  • 5V0_RAW → F3 → +5V0 → J3
  • 12V_RAW → F4 → +12V → J4

• J2/J3: source-only USB-C power outputs, passive 3 A Rp, no USB-PD and no data.
• J5: charge-only / sink-only USB-C input, no source/OTG and no Rp.
• J5 VBUS contacts go to USB_CHG_VBUS_RAW; CC1/CC2 go separately to the protected PD sink module; D+/D−/SBU are intentionally no-connect.

• MOD4: TBD protected sink-only USB-PD 3.0 trigger/controller module; ordinary 20 V / ≥3 A contract; no EPR required.
• MOD5: TBD genuine 5S buck-boost CC/CV charger module; 21.0 V maximum; default 1 A; optional 2 A only after pack/BMS approval.
• MOD6: TBD ≥30 V / ≥3 A reverse-current blocker unless MOD5 is independently proven to block reverse current in all states.
• F5: charge-path fuse, provisional 2.5 A element, final time-current and interrupt rating pending charger/fault validation.
• J6: external pack NTC connector; open, shorted, hot, or cold NTC must inhibit charging.
• J7: normally open charge-current jumper; default-open intent is 1 A; closing requests 2 A only after approval.
• R15 remains DNI/TBD between PD_20V_OK and CHARGER_EN_REQ until logic level/polarity is verified.

• J1: XT60 battery/BMS P+/P− interface.
• SW1: external maintained SPST switch loop; off-board switch must be rated at least 5 A at 30 VDC.
• J2: Raspberry Pi 400 5.1 V USB-C source-only output.
• J3: LCD 5 V USB-C source-only output.
• J4: 12 V KVM barrel connector; Tensility 54-00127; 5.5 × 2.1 mm; center-positive.
• J5: USB-C charge-only sink input.
• J6: external pack NTC connector, not a balance connector.
• J7: charge-current configuration jumper, not a balance connector.
• MOD4/MOD5/MOD6: generic charger subsystem module interfaces; exact parts/pinouts/footprints remain release blockers.

• Battery energy: approximately 74 Wh nominal.
• Discharge/load budget evidence includes a prior 37.3 W output-load budget.
• Charging budget evidence distinguishes a 21 W default charge mode and a 42 W optional mode.
• Optional 2 A charging remains disabled/DNI until the exact pack, BMS, charger, fuse, and thermals are approved.
• Charging injects into BAT_PROTECTED through F5 and must not bypass required protection and commissioning gates.

• Target mechanical envelope: 190 mm × 125 mm with rounded corners.
• Four-layer stack expectation:
  • L1 components/high-current routing.
  • L2 continuous ground plane.
  • L3 power distribution/low-current signals.
  • L4 secondary routing/ground copper.
  • Outer copper 2 oz, inner copper 1 oz.
• Use wide copper pours/planes for battery, ground, 5.1 V, 5 V, and 12 V paths.
• Keep charger thermally separated from output regulators.
• Preserve uninterrupted ground plane where practical.
• Add mounting holes, module-retention holes, XT60/cable strain relief, connector access, fuse replacement access, and switch access in a future layout phase.
• No layout validation has been completed in this migrated target.

• Edge-mounted user connectors where practical.
• Serviceable fuse access.
• Label J2 as Pi 5.1 V output, J3 as LCD 5 V output, J4 as KVM 12 V center-positive, and J5 as charge-only/sink-only USB-C.
• Provide labeled test points for: BAT_PROTECTED, VIN_SWITCHED/VIN_SW, VIN_PROTECTED, USB_CHG_VBUS_RAW, PD_20V, PD_20V_OK, CHARGER_OUT, CHARGER_EN_REQ, CHARGE_STATUS, FULL_STATUS, FAULT_STATUS, raw/fused output rails, PGOOD, and GND.

• Use an external/off-board BMS P+/P− interface for the first revision.
• Do not map the six-wire balance harness.
• J2/J3 are source-only USB-C outputs; J5 is a sink-only charge input.
• Use serviceable fuse holders where resolved.
• Retain generic charger module interfaces until authoritative module pinout, footprint, configuration, and safety data are available.
• Do not tie TPSM63606 VCC to a rail; evidence identifies the prior ERC as a library pin-type false positive.

• Exact MOD4/MOD5/MOD6 parts are not selected.
• MPS MEZS7-PDPowerBank-MP2652 was not accepted because public documentation did not provide enough mechanical/configuration information for a release-safe footprint.
• BMS common-port charging support and charge-current limits are unverified.
• Balance-wire order must be measured; colors/photos/diagrams are not proof.
• Current migrated target has 0 schematic components and 0 nets before schematic reconstruction.

• All five project files have been recreated.
• BOM and exact part metadata have been transferred.
• Schematic has been compared against parsed .flx evidence.
• All 44 expected nets have been accounted for or discrepancies documented.
• Every USB-C port has verified source-only or sink-only role.
• Balance harness remains unmapped unless measurements prove it.
• Charger and BMS uncertainties remain visible blockers.
• ERC results and unresolved issues are documented.
• PCB layout status is honest.
• No fabrication-ready claim is made without completed routing, DRC, thermal, mechanical, charging, backfeed, and battery-safety validation.

• 2026-07-24: Recreated this project file from migration source evidence as Phase 2 documentation only. No schematic or PCB layout work performed in this phase.