Project Startup Help

They’re still running. I’ll check final status once more and then give you the project links and current state so you’re not blocked waiting.
Created two separate PCB projects and started the split/place work in each:
Current status:
  • TX clone: RX circuitry removed, board-mounted XLR replaced with compact XLR harness pads, 25 × 80 mm / 4-layer target set, placement still running.
  • RX clone: TX circuitry removed, board-mounted XLR replaced with compact XLR harness pads, 25 mm width / 4-layer target set, placement still running.
  • Master project remains unchanged as the system/reference design.
Open item:
  • Both split-placement tasks are still running; they exceeded the wait window but are actively working on non-RF placement and verification.
Next step:
  • Open each project link later to review the completed thread result, or ask me to check their status again.
Check split projects
Check TX status
Check RX status
Fix failed split tasks
Compare split BOMs

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Prototype Revision A Verification Notes — Munkrofon
Status
Prototype Revision A — Not Production Validated
This file summarizes what was built, what the automated checks found, and what still blocks production readiness.
Schematic Built
The schematic now contains an exploratory two-unit wireless microphone prototype:
Transmitter
  • RTX1090R1 provisional DECT RF module block.
  • TLV320AIC3204 codec block.
  • THAT1580 balanced low-noise microphone preamp.
  • Female XLR input.
  • USB-C charging input.
  • BQ24074 charger / power-path IC.
  • AP2112K 3.3 V LDO.
  • MAX17048 fuel gauge.
  • TPS65131 ±5 V analog rails for the THAT1580.
  • Provisional antenna placeholder components for ANT1/ANT2.
Receiver
  • RTX1090R1 provisional DECT RF module block.
  • TLV320AIC3204 codec block.
  • THAT1646 true balanced line driver.
  • Male XLR output.
  • USB-C charging input.
  • BQ24074 charger / power-path IC.
  • AP2112K 3.3 V LDO.
  • MAX17048 fuel gauge.
  • TPS65131 ±5 V analog rails for the THAT1646.
  • Provisional antenna placeholder components for ANT1/ANT2.
Important Rev A Assumptions

Table


AreaAssumptionWhy it is provisional
RTX1090R1 footprintCreated from public datasheet pin table and LGA geometry.Official RTX CAD footprint/reference layout not available.
RF audio interfaceTLV320AIC3204 digital-audio/control pins mapped to plausible RTX1090 GPIO/audio-capable pins.Public RTX datasheet confirms digital audio capability but does not publish exact Sheerlink codec pin mapping.
AntennasNN02-224 wideband chip antenna placeholders used only to make antenna nets explicit.Official RTX1x90EVK antenna geometry, matching, spacing, diversity orientation, and modular-approval conditions are still required.
USB dataUSB-C D+/D− are protected by ESD devices but intentionally unused for Rev A charging-only USB.Final RTX firmware may require USB for programming, control, or test.
Fuel gaugeMAX17048 I²C tied to the provisional codec/control bus.Final host/firmware ownership of battery gauge is unknown.
Analog rails±5 V rails added for THAT1580 and THAT1646 after datasheet review showed dual supplies are required.Final audio headroom may require different analog rails.
Automated Check Results
After wiring fixes:
  • Floating-pin errors: cleared, except no current floating-pin findings in the final queried set.
  • Single-pin antenna-net errors: cleared by adding antenna placeholder components.
  • Remaining ERC category: Missing Power.
Remaining Missing-Power Findings
The remaining errors are treated as Rev A review items rather than silently ignored:

Table


Finding classAffected examplesInterpretation
System rails not recognized as drivenU5 VIN, U13 VIN, U11 VIN, U14 VIN, U1/U7 VBATRails are fed by BQ24074 OUT / battery path, but ERC does not treat that path as a formal power source in this schematic. Review during bring-up.
Codec internal-LDO output railsU2/U8 AVDD and DVDD on codec LDO-output/filter netsTLV320AIC3204 uses internal LDO/filter pins; ERC flags them because it does not understand the internal regulator. Confirm against TI power-sequencing app note before layout.
RTX module output pinsU1/U7 VDD_1V8, VDD_3V3, VDD_USB, VSUPPLYPublic RTX datasheet labels these as module outputs or optional supplies, but the provisional part/checker reports them as power inputs. Requires official RTX guidance.
THAT1646 VCC driven by RX_5VAU9 VCCRX_5VA is generated by TPS65131, but ERC does not recognize the generated rail as driven. Verify with power-stage simulation/bring-up.
Production-Readiness Dependencies
Before this can become production-intent:
  1. Official RTX1090/R1 hardware integration guide.
  2. Official RTX/RMED Sheerlink reference schematic, PCB layout, Gerbers, stackup, and BOM.
  3. Official antenna layout/matching/diversity requirements and modular-approval conditions.
  4. Exact Sheerlink audio pin mapping, clocking, codec support list, and firmware configuration.
  5. Written latency specification for the selected configuration.
  6. Confirmation of RTX1090 VDD/VBUS/VBAT ownership and whether external charger + module power pins are valid as drawn.
  7. Prototype measurement of analog rail ripple/noise and effect on mic preamp / line output noise floor.
  8. Audio performance verification: gain, clipping headroom, THD+N, SNR, noise floor, frequency response.
  9. RF range/coexistence testing and EMC pre-scan.
  10. Final PCB layout review against RTX reference design.
Pre-Layout Schematic Refinement Update — 2026-07-27
Completed Schematic Changes
  • Added TX XLR input protection: series resistors, BAV199 low-leakage clamps to GND/+5 V, PESD5V0 ESD clamps, RF shunt capacitors, and a differential RF capacitor.
  • Replaced both AP2112K direct-from-1S 3.3 V LDO rails with TPS63031 fixed 3.3 V buck-boost converters.
  • Added rail, audio, codec/control, output, and RF debug test points for TX and RX.
  • Marked MAX17048 fuel gauges U6 and U12 as optional/DNP via Exclude from Pick & Place and role notes.
  • Locked generic resistor, capacitor, and inductor package/rating/tolerance properties for pre-layout review.
  • Kept RF module, antenna implementation, codec/RF clocking, and RF pin mapping provisional pending RTX/RMED documentation.
Final ERC Status After Pre-Layout Refinement
Latest queried ERC status still reports 21 Missing Power errors. Floating-pin and single-pin-net issues are cleared in the checked set.
Explicit Missing-Power Justifications

Table


ERC finding classAffected examplesJustification / status
RTX1090R1 optional/output power pins modeled as inputsU1/U7 VDD_USB, VDD_3V3, VDD_1V8, VSUPPLY, VBUS_CHARGEThe provisional RTX1090R1 component was created from public data. Several pins are module outputs or optional integration pins, but the checker treats them as power inputs. Must be corrected when official RTX symbol/integration guide is available.
RTX1090R1 VBAT on system rail reported not drivenU1/U7 VBAT on TX_SYS/RX_SYSTX_SYS/RX_SYS are supplied by charger/power-path and battery, but ERC does not recognize the full canonical power-path as a driven source. Verify in bring-up; acceptable for Rev A schematic review but not a clean ERC.
Buck-boost VIN on system rail reported not drivenU5/U11/U13 VINThese are fed from TX_SYS/RX_SYS. Same power-source recognition limitation as above. Electrical connection is intentional.
Codec internal LDO/filter rails reported not drivenU2/U8 AVDD/DVDD on codec LDO/filter netsTLV320AIC3204 uses internal LDO/filter pins; ERC does not understand this regulator model. Confirm against TI power-sequencing guidance before PCB layout.
RX line-driver VCC on generated analog rail reported not drivenU9 VCC on RX_5VARX_5VA is generated by TPS65131, but ERC does not recognize the generated rail as driven. Verify during power simulation/bring-up.
Layout Readiness Recommendation
No — not ready for PCB layout yet.
Reasons:
  1. ERC is not clean; remaining Missing Power findings are justified but still unresolved at tool level.
  2. RTX/RMED RF integration documentation is still missing.
  3. Antenna implementation remains placeholder-only.
  4. RF/codec clocking and RF pin mapping remain provisional.
  5. The new switching rails and XLR protection should be reviewed in schematic form before committing to layout.
The schematic is substantially closer to layout readiness, but the next safe step is a short focused ERC/power-model cleanup and RF integration/documentation gate review, not PCB placement.
  • Status

  • Schematic Built

  • Transmitter

  • Receiver

  • Important Rev A Assumptions

  • Automated Check Results

  • Remaining Missing-Power Findings

  • Production-Readiness Dependencies

  • Pre-Layout Schematic Refinement Update — 2026-07-27

  • Completed Schematic Changes

  • Final ERC Status After Pre-Layout Refinement

  • Explicit Missing-Power Justifications

  • Layout Readiness Recommendation