Project Startup Help
Table
| Area | Assumption | Why it is provisional |
|---|---|---|
| RTX1090R1 footprint | Created from public datasheet pin table and LGA geometry. | Official RTX CAD footprint/reference layout not available. |
| RF audio interface | TLV320AIC3204 digital-audio/control pins mapped to plausible RTX1090 GPIO/audio-capable pins. | Public RTX datasheet confirms digital audio capability but does not publish exact Sheerlink codec pin mapping. |
| Antennas | NN02-224 wideband chip antenna placeholders used only to make antenna nets explicit. | Official RTX1x90EVK antenna geometry, matching, spacing, diversity orientation, and modular-approval conditions are still required. |
| USB data | USB-C D+/D− are protected by ESD devices but intentionally unused for Rev A charging-only USB. | Final RTX firmware may require USB for programming, control, or test. |
| Fuel gauge | MAX17048 I²C tied to the provisional codec/control bus. | Final host/firmware ownership of battery gauge is unknown. |
| Analog rails | ±5 V rails added for THAT1580 and THAT1646 after datasheet review showed dual supplies are required. | Final audio headroom may require different analog rails. |
Table
| Finding class | Affected examples | Interpretation |
|---|---|---|
| System rails not recognized as driven | U5 VIN, U13 VIN, U11 VIN, U14 VIN, U1/U7 VBAT | Rails are fed by BQ24074 OUT / battery path, but ERC does not treat that path as a formal power source in this schematic. Review during bring-up. |
| Codec internal-LDO output rails | U2/U8 AVDD and DVDD on codec LDO-output/filter nets | TLV320AIC3204 uses internal LDO/filter pins; ERC flags them because it does not understand the internal regulator. Confirm against TI power-sequencing app note before layout. |
| RTX module output pins | U1/U7 VDD_1V8, VDD_3V3, VDD_USB, VSUPPLY | Public RTX datasheet labels these as module outputs or optional supplies, but the provisional part/checker reports them as power inputs. Requires official RTX guidance. |
| THAT1646 VCC driven by RX_5VA | U9 VCC | RX_5VA is generated by TPS65131, but ERC does not recognize the generated rail as driven. Verify with power-stage simulation/bring-up. |
Table
| ERC finding class | Affected examples | Justification / status |
|---|---|---|
| RTX1090R1 optional/output power pins modeled as inputs | U1/U7 VDD_USB, VDD_3V3, VDD_1V8, VSUPPLY, VBUS_CHARGE | The provisional RTX1090R1 component was created from public data. Several pins are module outputs or optional integration pins, but the checker treats them as power inputs. Must be corrected when official RTX symbol/integration guide is available. |
| RTX1090R1 VBAT on system rail reported not driven | U1/U7 VBAT on TX_SYS/RX_SYS | TX_SYS/RX_SYS are supplied by charger/power-path and battery, but ERC does not recognize the full canonical power-path as a driven source. Verify in bring-up; acceptable for Rev A schematic review but not a clean ERC. |
| Buck-boost VIN on system rail reported not driven | U5/U11/U13 VIN | These are fed from TX_SYS/RX_SYS. Same power-source recognition limitation as above. Electrical connection is intentional. |
| Codec internal LDO/filter rails reported not driven | U2/U8 AVDD/DVDD on codec LDO/filter nets | TLV320AIC3204 uses internal LDO/filter pins; ERC does not understand this regulator model. Confirm against TI power-sequencing guidance before PCB layout. |
| RX line-driver VCC on generated analog rail reported not driven | U9 VCC on RX_5VA | RX_5VA is generated by TPS65131, but ERC does not recognize the generated rail as driven. Verify during power simulation/bring-up. |
Status
Schematic Built
Transmitter
Receiver
Important Rev A Assumptions
Automated Check Results
Remaining Missing-Power Findings
Production-Readiness Dependencies
Pre-Layout Schematic Refinement Update — 2026-07-27
Completed Schematic Changes
Final ERC Status After Pre-Layout Refinement
Explicit Missing-Power Justifications
Layout Readiness Recommendation