Sovereign Edge Aggregator PCB Design

flux

0:25

Thought for a moment

I’ll parse the updated CM5 pinout CSV now, verify whether it includes all three 100-pin connector sections, then update the CM5 symbol spec and proceed with safe schematic planning from the complete pin map.

flux

3:29

Thought for 9 sec

1/4 Parse updated CM5 CSV and verify U13-A/U13-B/U13-C coverage

Thought for 5 sec

Running code.

Code executed.

Thought for 12 sec

Thought for 7 sec

Thought for 18 sec

Thought for 9 sec

Thought for a moment

I parsed the updated CM5 CSV and confirmed it still contains only U13-B pins 101–200: U13-A pins 1–100 and U13-C pins 201–300 are still missing. I updated Radxa CM5 3x100 Connector Symbol Specification and BOM Preview and Net Constraints with the updated parse result.
Current state:
  • Board outline and 6-layer layout are configured.
  • Raw chip-down RK3588 was removed from the schematic.
  • Candidate BOM parts are identified for FPGA, ATECC608B, INA260, RTL8211F, M.2 Key-M, TPS54331, and LDOs.
  • No active components were added because the CM5 300-pin SoM symbol is still incomplete; adding them now would leave floating ICs and fail ERC.
Remaining blocker:
  • Need full CM5 pinout including U13-A, U13-B, U13-C, or one CSV per connector section.
  • Need exact mating connector MPNs/footprints from the Radxa CM5 mechanical/BOM files.
Once those are available, the next step is to create/import the CM5 3×100 connector symbol, then add and wire the core carrier blocks.
Create placeholder connector
Find connector MPNs
Show required CSV columns
Use U13-B only
Run ERC/DRC

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Sovereign Edge Aggregator PCB (Tier 2 Node) — Project Specification
Product Intent
Professional industrial edge aggregation PCB for a Tier 2 node. The board hosts Linux edge compute, a deterministic FPGA security/math engine, secure key storage, local ledger storage, dual Gigabit Ethernet, redundant input power, passive cooling provisions, and a status LED matrix.
Mechanical Target
  • Board outline: 100 mm x 80 mm rectangular PCB.
  • Style: industrial, robust, clean routing, professional labels.
  • Cooling: large thermal pad/copper area for SoC/module and M.2 NVMe region; optional fan header.
  • User-facing connectors at board edges: USB-C PD input, DC jack, two RJ45 Ethernet ports, M.2 NVMe slot, fan header/debug headers as needed.
Core Functional Blocks
  1. Compute / Linux Host
    • Rockchip RK3588S compute module with 8 GB LPDDR4X.
    • Role: Linux Host, GraalVM Runtime, Vogon ProofDB (SQLite/immudb).
    • Critical open item: exact compute module MPN and connector pinout required before schematic wiring.
  2. Deterministic Engine
    • Lattice CrossLink-NX FPGA, LIFCL-40 family.
    • Role label on silkscreen: Quantum Determinism Engine.
    • Function: Ring Zero hardware, Hamiltonian math, hash chain sealer.
    • Interface to SoC: high-speed parallel bus with controlled-impedance routing and length matching.
  3. Security
    • Microchip ATECC608B secure element.
    • Role label on silkscreen: Post-Quantum Trust Anchor.
    • Interface: expected I2C to SoC and/or FPGA supervisory bus, exact bus owner TBD.
  4. Storage
    • 128 GB industrial eMMC.
    • M.2 NVMe M-key slot for local ledger expansion.
    • Critical note: RK3588S module must expose PCIe lanes for NVMe; exact module connector pinout controls routing feasibility.
  5. Networking
    • Dual Gigabit Ethernet PHYs, RTL8211F class, with magnetic isolation RJ45 connectors.
    • Port 1 label: Uplink to Tier 1.
    • Port 2 label: Downlink to Tier 3.
    • PTP hardware timestamping requirement must be validated against MAC/PHY support in the selected RK3588S module and Linux driver; PHY-only timestamping support is not assumed.
  6. Power
    • USB-C PD input target: 15 W minimum negotiated power.
    • 12 V DC jack input for redundancy.
    • Power path requires ideal-diode / power-mux behavior, input protection, hot-plug/inrush management, and buck regulators sized from the actual power budget.
    • Separate power domains/planes for SoC Linux domain and FPGA deterministic domain while maintaining a solid shared ground reference.
  7. Status LED Matrix
    • Indicators for Epoch Health, Sync Status, and Power Fidelity.
    • Preferred implementation: low-current LED matrix driven by GPIO expander or SoC/FPGA GPIO with current-limited LEDs.
High-Speed / PCB Stackup Requirements
  • Minimum recommended stackup: 6 layers because of PCIe/NVMe, dual Gigabit Ethernet, high-speed SoC-FPGA bus, and multiple power domains.
  • Preferred layer intent:
    • L1: high-speed signal + components
    • L2: solid GND reference plane
    • L3: inner signal / controlled bus routing
    • L4: split or regioned power plane for SoC, FPGA, I/O rails
    • L5: solid GND reference plane
    • L6: secondary signal + passives
  • Controlled impedance targets to verify with fabricator stackup:
    • PCIe/NVMe: 85 ohm differential typical
    • Gigabit Ethernet MDI pairs: 100 ohm differential
    • SoC-FPGA parallel bus: 50 ohm single-ended with matched data/control groups
  • Do not split GND under high-speed traces; keep return paths continuous.
Initial Power Budget Assumptions
These are planning assumptions until exact module datasheets are selected.
  • RK3588S compute module: 8 to 12 W peak design allowance.
  • CrossLink-NX LIFCL-40 FPGA domain: 1.5 to 3 W allowance depending on fabric utilization and I/O activity.
  • Dual RTL8211F PHY + magnetics: 0.8 to 1.5 W allowance.
  • NVMe M.2 slot: reserve up to 3.3 V at 3 A peak unless reduced by chosen slot power limit.
  • eMMC + secure element + LEDs + fan/control: 0.5 to 2 W allowance.
  • Total board-level design target: USB-C PD 15 W is marginal if NVMe and fan are active; DC jack should support higher sustained power. Recommend designing the power tree for at least 25 W input capability while allowing USB-C PD 15 W derated operation mode.
Schematic Capture Gate
Do not wire the RK3588S compute module, LIFCL-40, Ethernet PHYs, eMMC, or NVMe slot from memory. Schematic capture requires exact library parts or exact datasheets/pinouts. If Flux library parts are missing, request/import part libraries before wiring.
Open Decisions
  • Exact RK3588S compute module vendor/MPN and connector pinout.
  • Whether eMMC is on the compute module or on the carrier PCB.
  • Whether Ethernet MACs are exposed as RGMII from module, and which pins are available for dual PHYs.
  • Which USB-C PD controller and power mux architecture to use.
  • Whether status LED matrix is driven by SoC GPIO, FPGA GPIO, or an I2C GPIO expander.
  • Target PCB manufacturer stackup for impedance calculation.

    Product Intent

    Mechanical Target

    Core Functional Blocks

    High-Speed / PCB Stackup Requirements

    Initial Power Budget Assumptions

    Schematic Capture Gate

    Open Decisions

Documents

    Sovereign Edge Aggregator PCB (Tier 2 Node) — Project Specification

    Sovereign Edge Aggregator — Initial Power Budget and Rail Plan

    Component Selection Status — Sovereign Edge Aggregator

    ROCK 5B Carrier Feasibility and Layout Plan

    True RK3588 Compute-Module Carrier Plan — Path B

    Radxa CM5 3x100 Connector Symbol Specification

    BOM Preview and Net Constraints — Sovereign Edge Aggregator Carrier

Assets

Assets are files uploaded to this project which can be used in various ways.

Sovereign Edge Aggregator Tier 2 Node thumbnail
Industrial 100 mm x 80 mm 6-layer RK3588S compute-module carrier for the Sovereign Edge Aggregator, targeting Radxa CM5-class SoM, CrossLink-NX Ring Zero FPGA, ATECC608B trust anchor, INA260 energy metering, NVMe, dual Gigabit Ethernet, and controlled-impedance routing.

Properties

Properties describe core aspects of the project.

Pricing & Availability

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Controls