Sovereign Edge Aggregator PCB Design
Worked for 1 min 55 sec
Updated the production baseline to Toradex Verdin iMX95 across:
- EcoSynQ Tier-3 Witness Node ASIC/SBC Architecture
- i.MX 95 Tier-3 Production Design Specification
- Rejected 4-Layer i.MX 95 Spec Correction Checklist
The checklist now requires Verdin-specific gates: exact Verdin iMX95 SKU, Toradex datasheet/carrier guide, Verdin connector footprint and mechanical model, Toradex power requirements, thermal guidance, and confirmation of Ethernet/PTP, TPM, Wi-Fi/BT, and NVMe implementation before schematic capture.
Create a Verdin iMX95 bring-up and procurement checklist from the updated gates.
Thought for 5 sec
I’ll create a Verdin iMX95 bring-up and procurement checklist from the updated gates, covering documents to obtain, parts to order, first-power validation, secure boot, Ethernet/PTP, NVMe, thermal, and sealed-node tests.
Worked for 2 mins 2 sec
It covers procurement, Toradex documentation gates, carrier-side part selection, pre-schematic release criteria, first-article power-up, BSP boot, TPM/ATECC security validation, NVMe, Ethernet/PTP, wireless, thermal testing, and production-lock checks. Critical next gate: select the exact Toradex Verdin iMX95 SKU before schematic capture.
Select Verdin SKU
Research Toradex docs
Create power budget
Plan carrier schematic
Fix wrong component
Refine this doc
Ask about this doc
Sovereign Edge Aggregator PCB (Tier 2 Node) — Project Specification
Product Intent
Professional industrial edge aggregation PCB for a Tier 2 node. The board hosts Linux edge compute, a deterministic FPGA security/math engine, secure key storage, local ledger storage, dual Gigabit Ethernet, redundant input power, passive cooling provisions, and a status LED matrix.
Mechanical Target
- Board outline: 100 mm x 80 mm rectangular PCB.
- Style: industrial, robust, clean routing, professional labels.
- Cooling: large thermal pad/copper area for SoC/module and M.2 NVMe region; optional fan header.
- User-facing connectors at board edges: USB-C PD input, DC jack, two RJ45 Ethernet ports, M.2 NVMe slot, fan header/debug headers as needed.
Core Functional Blocks
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Compute / Linux Host
- Rockchip RK3588S compute module with 8 GB LPDDR4X.
- Role: Linux Host, GraalVM Runtime, Vogon ProofDB (SQLite/immudb).
- Critical open item: exact compute module MPN and connector pinout required before schematic wiring.
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Deterministic Engine
- Lattice CrossLink-NX FPGA, LIFCL-40 family.
- Role label on silkscreen: Quantum Determinism Engine.
- Function: Ring Zero hardware, Hamiltonian math, hash chain sealer.
- Interface to SoC: high-speed parallel bus with controlled-impedance routing and length matching.
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Security
- Microchip ATECC608B secure element.
- Role label on silkscreen: Post-Quantum Trust Anchor.
- Interface: expected I2C to SoC and/or FPGA supervisory bus, exact bus owner TBD.
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Storage
- 128 GB industrial eMMC.
- M.2 NVMe M-key slot for local ledger expansion.
- Critical note: RK3588S module must expose PCIe lanes for NVMe; exact module connector pinout controls routing feasibility.
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Networking
- Dual Gigabit Ethernet PHYs, RTL8211F class, with magnetic isolation RJ45 connectors.
- Port 1 label: Uplink to Tier 1.
- Port 2 label: Downlink to Tier 3.
- PTP hardware timestamping requirement must be validated against MAC/PHY support in the selected RK3588S module and Linux driver; PHY-only timestamping support is not assumed.
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Power
- USB-C PD input target: 15 W minimum negotiated power.
- 12 V DC jack input for redundancy.
- Power path requires ideal-diode / power-mux behavior, input protection, hot-plug/inrush management, and buck regulators sized from the actual power budget.
- Separate power domains/planes for SoC Linux domain and FPGA deterministic domain while maintaining a solid shared ground reference.
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Status LED Matrix
- Indicators for Epoch Health, Sync Status, and Power Fidelity.
- Preferred implementation: low-current LED matrix driven by GPIO expander or SoC/FPGA GPIO with current-limited LEDs.
High-Speed / PCB Stackup Requirements
- Minimum recommended stackup: 6 layers because of PCIe/NVMe, dual Gigabit Ethernet, high-speed SoC-FPGA bus, and multiple power domains.
- Preferred layer intent:
- L1: high-speed signal + components
- L2: solid GND reference plane
- L3: inner signal / controlled bus routing
- L4: split or regioned power plane for SoC, FPGA, I/O rails
- L5: solid GND reference plane
- L6: secondary signal + passives
- Controlled impedance targets to verify with fabricator stackup:
- PCIe/NVMe: 85 ohm differential typical
- Gigabit Ethernet MDI pairs: 100 ohm differential
- SoC-FPGA parallel bus: 50 ohm single-ended with matched data/control groups
- Do not split GND under high-speed traces; keep return paths continuous.
Initial Power Budget Assumptions
These are planning assumptions until exact module datasheets are selected.
- RK3588S compute module: 8 to 12 W peak design allowance.
- CrossLink-NX LIFCL-40 FPGA domain: 1.5 to 3 W allowance depending on fabric utilization and I/O activity.
- Dual RTL8211F PHY + magnetics: 0.8 to 1.5 W allowance.
- NVMe M.2 slot: reserve up to 3.3 V at 3 A peak unless reduced by chosen slot power limit.
- eMMC + secure element + LEDs + fan/control: 0.5 to 2 W allowance.
- Total board-level design target: USB-C PD 15 W is marginal if NVMe and fan are active; DC jack should support higher sustained power. Recommend designing the power tree for at least 25 W input capability while allowing USB-C PD 15 W derated operation mode.
Schematic Capture Gate
Do not wire the RK3588S compute module, LIFCL-40, Ethernet PHYs, eMMC, or NVMe slot from memory. Schematic capture requires exact library parts or exact datasheets/pinouts. If Flux library parts are missing, request/import part libraries before wiring.
Open Decisions
- Exact RK3588S compute module vendor/MPN and connector pinout.
- Whether eMMC is on the compute module or on the carrier PCB.
- Whether Ethernet MACs are exposed as RGMII from module, and which pins are available for dual PHYs.
- Which USB-C PD controller and power mux architecture to use.
- Whether status LED matrix is driven by SoC GPIO, FPGA GPIO, or an I2C GPIO expander.
- Target PCB manufacturer stackup for impedance calculation.
Product Intent
Mechanical Target
Core Functional Blocks
High-Speed / PCB Stackup Requirements
Initial Power Budget Assumptions
Schematic Capture Gate
Open Decisions
