Sovereign Edge Aggregator PCB Design

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0:25

Thought for a moment

I’ll parse the updated CM5 pinout CSV now, verify whether it includes all three 100-pin connector sections, then update the CM5 symbol spec and proceed with safe schematic planning from the complete pin map.

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3:29

Thought for 9 sec

1/4 Parse updated CM5 CSV and verify U13-A/U13-B/U13-C coverage

Thought for 5 sec

Running code.

Code executed.

Thought for 12 sec

Thought for 7 sec

Thought for 18 sec

Thought for 9 sec

Thought for a moment

I parsed the updated CM5 CSV and confirmed it still contains only U13-B pins 101–200: U13-A pins 1–100 and U13-C pins 201–300 are still missing. I updated Radxa CM5 3x100 Connector Symbol Specification and BOM Preview and Net Constraints with the updated parse result.
Current state:
  • Board outline and 6-layer layout are configured.
  • Raw chip-down RK3588 was removed from the schematic.
  • Candidate BOM parts are identified for FPGA, ATECC608B, INA260, RTL8211F, M.2 Key-M, TPS54331, and LDOs.
  • No active components were added because the CM5 300-pin SoM symbol is still incomplete; adding them now would leave floating ICs and fail ERC.
Remaining blocker:
  • Need full CM5 pinout including U13-A, U13-B, U13-C, or one CSV per connector section.
  • Need exact mating connector MPNs/footprints from the Radxa CM5 mechanical/BOM files.
Once those are available, the next step is to create/import the CM5 3×100 connector symbol, then add and wire the core carrier blocks.
Create placeholder connector
Find connector MPNs
Show required CSV columns
Use U13-B only
Run ERC/DRC

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Radxa CM5 3x100 Connector Symbol Specification
Purpose
This project requires a custom schematic symbol named Radxa_CM5_3x100_Edge_Connector for a true Radxa CM5-class RK3588S compute-module carrier board. The full symbol requires all three connector sections for 300 pins.
Required Symbol
  • Symbol name: Radxa_CM5_3x100_Edge_Connector
  • Pin count: 300 pins total.
  • Connector grouping: 3 rows / sections of 100 pins each.
    • U13-A: pins 1-100 — not present in the parsed CSV data.
    • U13-B: pins 101-200 — present in the parsed CSV data.
    • U13-C: pins 201-300 — not present in the parsed CSV data.
  • Add component property:
    • Note: Refer to Radxa CM5 V2.21 Pinout CSV for Alt Functions.
Required Pin Groups
Group A — Power
  • VCC_SYSIN
  • VCC_3V3
  • VCC_1V8
  • GND
  • Any special power-assist pins, including the U13-B pin 106 5V_HDMI note.
Group B — High Speed
  • PCIe signals such as PCIE20_0_REFCLKP/N, PCIE20_0_RXP/N, PCIE20_0_TXP/N.
  • USB3 SuperSpeed signals.
  • MIPI DPHY signals.
  • HDMI high-speed signals if exposed.
Group C — Deterministic I/O
  • GPIO pins usable for FPGA Ring Zero bus.
  • SPI pins.
  • I2C pins.
  • UART pins.
  • PWM pins.
  • Important: GPIO voltage domains may be 1.8 V or 3.3 V and must be checked before wiring to the FPGA.
Group D — Management
  • I2C_SDA / I2C_SCL buses.
  • RESET / PERST / PROG_B candidates.
  • CLKREQ / PERST / wake pins.
  • Power-good, enable, boot, and interrupt management pins.
Updated CSV Parse Result
The newly uploaded radxa_cm5_v2210_pinout_UPDATED.csv was parsed.
  • Parsed rows: 100.
  • Unique pins: 100.
  • Explicit U13-A/U13-B/U13-C labels: none found.
  • Inferred connector sections by pin number:
    • U13-A pins 1-100: absent; missing 1-100.
    • U13-B pins 101-200: present; 100 pins; no missing pins.
    • U13-C pins 201-300: absent; missing 201-300.
  • Key signal groups in the updated CSV:
    • Power/GND: 31 pins.
    • PCIe: 11 pins.
    • RGMII/SGMII/MDIO/MDC: 0 pins.
    • SPI: 5 pins.
    • I2C: 4 pins.
    • UART: 1 pin.
    • PWM: 3 pins.
    • GPIO: 5 pins.
  • Parse note: CSV is ragged; pin 200 row appears short/truncated.
Extracted U13-B Pin Mapping From Uploaded CSV
Only U13-B is available in the uploaded CSV. Treat this as partial data until U13-A and U13-C are supplied.

U13-B Power / Ground

PinCM5 SignalNotes
1065V_HDMIIf VCC_SYSIN provides 5 V, this pin can be NC; if VCC_SYSIN is less than 5 V, carrier must provide 5 V to CM5.
107GNDGround
108GNDGround
113GNDGround
114GNDGround
119GNDGround
120GNDGround
125GNDGround
126GNDGround
131GNDGround
132GNDGround
137GNDGround
138GNDGround
144GNDGround
150GNDGround
155GNDGround
156GNDGround
161GNDGround
162GNDGround
167GNDGround
168GNDGround
173GNDGround
174GNDGround
179GNDGround
180GNDGround
185GNDGround
186GNDGround
191GNDGround
192GNDGround
197GNDGround
198GNDGround

U13-B PCIe / High-Speed

PinCM5 SignalFunction
102PCIE20X1_2_CLKREQN_M0PCIe clock request / alt GPIO/SPI/I2C
109PCIE20X1_2_PERSTN_M0PCIe reset / alt GPIO/SPI/UART/PWM
110PCIE20_0_REFCLKPPCIe reference clock positive
112PCIE20_0_REFCLKNPCIe reference clock negative
116PCIE20_0_RXPPCIe RX positive, alt SATA30_0_RXP
118PCIE20_0_RXNPCIe RX negative, alt SATA30_0_RXN
122PCIE20_0_TXPPCIe TX positive, alt SATA30_0_TXP
124PCIE20_0_TXNPCIe TX negative, alt SATA30_0_TXN
151HDMI_TX0_CEC_PORTAlt PCIE20X1_2_PERSTN_M1, I2C8 SDA, SPI3 CS1, GPIO4_C1
199HDMI_TX0_SDA_5VAlt PCIE20X1_2_WAKEN_M1, I2C8 SCL, SPI3 CS0, GPIO4_C0
200HDMI_TX0_SCL_5VAlt PCIE20X1_2_CLKREQN_M1, I2C5 SDA, SPI3 CLK, GPIO4_B7

U13-B Candidate SPI / I2C / GPIO Pins

PinPrimary CM5 SignalUseful Alt Functions
102PCIE20X1_2_CLKREQN_M0I2C5_SCL_M0, SPI3_MOSI_M3, GPIO3_C7
109PCIE20X1_2_PERSTN_M0UART4_TX_M1, PWM9_M2, SPI0_MISO_M3, GPIO3_D1
149NCI2C5_SCL_M1, PWM13_M1, SPI3_MOSI_M1, GPIO4_B6
151HDMI_TX0_CEC_PORTI2C8_SDA_M3, PWM6_M1, SPI3_CS1_M1, GPIO4_C1
153HDMI_TX0_HPDSPI2_MOSI_M0, GPIO1_A5
199HDMI_TX0_SDA_5VI2C8_SCL_M3, SPI3_CS0_M1, GPIO4_C0
200HDMI_TX0_SCL_5VI2C5_SDA_M1, SPI3_CLK_M1, GPIO4_B7
Critical Finding
The updated CSV still contains only U13-B, pins 101-200. It does not include U13-A pins 1-100 or U13-C pins 201-300. Therefore a complete 300-pin symbol cannot be generated with full confidence from the current data.
Required Next Input
Provide the complete CM5 pinout as a CSV that includes U13-A, U13-B, and U13-C, or provide the original XLSX converted into one CSV per connector section. Also provide the mating connector footprint/library files or exact connector MPNs from Radxa CM5 mechanical documentation.

    Purpose

    Required Symbol

    Required Pin Groups

    Group A — Power

    Group B — High Speed

    Group C — Deterministic I/O

    Group D — Management

    Updated CSV Parse Result

    Extracted U13-B Pin Mapping From Uploaded CSV

    U13-B Power / Ground

    U13-B PCIe / High-Speed

    U13-B Candidate SPI / I2C / GPIO Pins

    Critical Finding

    Required Next Input

Documents

    Sovereign Edge Aggregator PCB (Tier 2 Node) — Project Specification

    Sovereign Edge Aggregator — Initial Power Budget and Rail Plan

    Component Selection Status — Sovereign Edge Aggregator

    ROCK 5B Carrier Feasibility and Layout Plan

    True RK3588 Compute-Module Carrier Plan — Path B

    Radxa CM5 3x100 Connector Symbol Specification

    BOM Preview and Net Constraints — Sovereign Edge Aggregator Carrier

Assets

Assets are files uploaded to this project which can be used in various ways.

Sovereign Edge Aggregator Tier 2 Node thumbnail
Industrial 100 mm x 80 mm 6-layer RK3588S compute-module carrier for the Sovereign Edge Aggregator, targeting Radxa CM5-class SoM, CrossLink-NX Ring Zero FPGA, ATECC608B trust anchor, INA260 energy metering, NVMe, dual Gigabit Ethernet, and controlled-impedance routing.

Properties

Properties describe core aspects of the project.

Pricing & Availability

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Controls