Sovereign Edge Aggregator PCB Design
0:25
Thought for a moment
I’ll parse the updated CM5 pinout CSV now, verify whether it includes all three 100-pin connector sections, then update the CM5 symbol spec and proceed with safe schematic planning from the complete pin map.
3:29
Thought for 9 sec
1/4 Parse updated CM5 CSV and verify U13-A/U13-B/U13-C coverage
Thought for 5 sec
Running code.
Code executed.
Thought for 12 sec
Thought for 7 sec
Thought for 18 sec
Thought for 9 sec
Thought for a moment
I parsed the updated CM5 CSV and confirmed it still contains only U13-B pins 101–200: U13-A pins 1–100 and U13-C pins 201–300 are still missing. I updated Radxa CM5 3x100 Connector Symbol Specification and BOM Preview and Net Constraints with the updated parse result.
Current state:
- Board outline and 6-layer layout are configured.
- Raw chip-down RK3588 was removed from the schematic.
- Candidate BOM parts are identified for FPGA, ATECC608B, INA260, RTL8211F, M.2 Key-M, TPS54331, and LDOs.
- No active components were added because the CM5 300-pin SoM symbol is still incomplete; adding them now would leave floating ICs and fail ERC.
Remaining blocker:
- Need full CM5 pinout including U13-A, U13-B, U13-C, or one CSV per connector section.
- Need exact mating connector MPNs/footprints from the Radxa CM5 mechanical/BOM files.
Once those are available, the next step is to create/import the CM5 3×100 connector symbol, then add and wire the core carrier blocks.
Create placeholder connector
Find connector MPNs
Show required CSV columns
Use U13-B only
Run ERC/DRC
Finished working
Refine this doc
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BOM Preview and Net Constraints — Sovereign Edge Aggregator Carrier
BOM Preview Status
This is a pre-schematic BOM preview. Components are not yet placed in the schematic because the Radxa CM5 3x100 SoM symbol is incomplete: the uploaded CSV extraction contains only U13-B pins 101-200. Adding active components now without the CM5 symbol would create floating, unwired parts and would not satisfy ERC.
Selected / Candidate Parts
| Function | Candidate Part | MPN | Flux UID | Package / Footprint | Status |
|---|---|---|---|---|---|
| RK3588S SoM | Radxa CM5 custom symbol | Radxa CM5 | Not in library | 3 x 100-pin B2B connector module | Must create/import custom part |
| FPGA Ring Zero Engine | Lattice CrossLink-NX | LIFCL-40-7BG256C | de419498-65bf-485b-b4f0-4b6294e538cd | CABGA-256 14 x 14 mm, 0.80 mm pitch | Found; note not QFN-256 |
| Secure Element | Microchip Trust Anchor | ATECC608B-TNGTLS | 474b7e80-de89-4804-9fa3-c5f26e0ec8cf | SOIC-8 | Found |
| Input Power Monitor | TI INA260 | INA260AIPWR | fb06733f-c89a-4944-bc4d-37dea6f7d168 | TSSOP-16 | Found |
| Ethernet PHY x2 | Realtek GbE PHY | RTL8211F-CG | 0f498d95-4a4e-44ff-b4c3-e2ca9388f5de | WQFN-40 exposed pad | Found |
| NVMe Connector | M.2 Key M slot | Attend 123A-40M00 | b92b3b3a-c258-43d5-8695-2c4eca65b62e | M-Key M.2 67-position | Found |
| FPGA Buck Regulator | TI Buck | TPS54331DR | 6d366b0a-e22a-40e9-bf0e-4b097e20af40 | SOIC-8 | Found |
| 3.3 V LDO | Diodes Inc. regulator | ZMR330FTA | 2cd05075-00e3-4acb-98b5-c10835fb6314 | SOT-23-3 | Candidate; verify current/thermal before use |
| 1.8 V LDO | LP3985 type | LP3985-18B3F | 17e2f7ea-4d4b-493a-94e6-41aca1c34313 | SOT-23-3 | Candidate; verify vendor/current before use |
| B2B Connector | Panasonic AXK | AXK600347YG | 88f84e19-b013-4b7c-b6fa-6083f9bf2b8c | 100P 0.50 mm SMT | Candidate until CM5 exact connector MPN confirmed |
| B2B Connector | Hirose DF40 | DF40C-100DS-0.4V(51) | 677f89fd-d2a7-414f-9844-3d72d624d05d | 100P 0.40 mm SMT | Candidate until CM5 exact connector MPN confirmed |
Missing Footprint / Symbol Flags
- Radxa CM5 SoM symbol/footprint: missing. This is the primary blocker.
- CM5 U13-A and U13-C connector pinout sections: missing from uploaded CSV extraction.
- Exact mating connector MPNs: not confirmed.
- LIFCL-40-7BG256C: footprint exists, but requested QFN-256 package is inconsistent with available CABGA-256 library part.
- 3.3 V / 1.8 V regulators: candidate parts found, but current and thermal requirements must be finalized after the power budget is updated from actual rail loads.
Net Classes / Constraint Plan
HIGH_SPEED_DIFFPurpose: PCIe and Ethernet differential pairs.
- PCIe/NVMe:
- Nets:
PCIE20_0_REFCLKP/N,PCIE20_0_TXP/N,PCIE20_0_RXP/N,PCIE_CLKREQN,PCIE_PERSTN. - Target impedance: confirm with CM5 reference design and fabricator. User requested 100 ohm differential; PCIe commonly uses 85 ohm differential, so this must be resolved before routing.
- Pair skew: keep within PCIe reference-design limits once exact stackup is known.
- Avoid vias where practical; match vias in each pair.
- Nets:
- Ethernet MDI:
- Nets: PHY-to-magnetics and magnetics-to-RJ45 pairs.
- Target impedance: 100 ohm differential.
- Keep TX/RX pair spacing controlled and keep away from switching regulator nodes.
DETERMINISTIC_IOPurpose: FPGA-to-CM5 Ring Zero bus.
- Nets: proposed
RZ_D[0..31],RZ_CLK,RZ_VALID,RZ_READY,RZ_IRQ,RZ_RESET. - Constraint: length match < 5 mm within bus group.
- Routing rule: no vias if possible; route on a layer referenced to continuous GND.
- Critical issue: currently extracted U13-B only exposes a small number of GPIO/SPI/I2C alternatives. A full 32-bit bus must be validated against U13-A/U13-C pinout before committing.
POWER_SENSEPurpose: INA260 measured input path.
- Nets:
VIN_RAW,VIN_MON,SYS_IN. - Route as a Kelvin/current path per INA260 datasheet and place monitor near input power entry.
- Keep I2C lines away from switching nodes.
LOW_SPEED_CTRLPurpose: I2C, SPI config, reset, IRQ, MDIO/MDC.
- Nets:
I2C_SEC_SDA/SCL,I2C_PWR_SDA/SCL,SPI_FPGA_MOSI/MISO/SCK/CS,FPGA_PROG_B,FPGA_DONE,ETH_MDIO,ETH_MDC. - Pull-ups required on I2C and MDIO as specified by selected voltage domain.
Extracted U13-B Constraints From Updated CSV
- U13-B contains PCIe20_0 x1 pins for NVMe candidate routing:
- 110
PCIE20_0_REFCLKP - 112
PCIE20_0_REFCLKN - 116
PCIE20_0_RXP - 118
PCIE20_0_RXN - 122
PCIE20_0_TXP - 124
PCIE20_0_TXN
- 110
- U13-B includes control alternatives:
- 102
PCIE20X1_2_CLKREQN_M0, alt I2C5_SCL/SPI3_MOSI/GPIO3_C7. - 109
PCIE20X1_2_PERSTN_M0, alt UART4_TX/PWM9/SPI0_MISO/GPIO3_D1. - 199 alt
PCIE20X1_2_WAKEN_M1, I2C8_SCL, SPI3_CS0, GPIO4_C0. - 200 alt
PCIE20X1_2_CLKREQN_M1, I2C5_SDA, SPI3_CLK, GPIO4_B7.
- 102
- No RGMII/SGMII/MDIO/MDC rows were present in the uploaded U13-B extract.
Updated CSV Parse Result
- Updated CSV still contains only 100 unique pins.
- Inferred present section: U13-B pins 101-200.
- Missing sections: U13-A pins 1-100 and U13-C pins 201-300.
- RGMII/SGMII/MDIO/MDC candidates remain absent from the parsed file, so dual Ethernet PHY wiring cannot be assigned yet.
- The deterministic 32-bit FPGA bus cannot be allocated from the available U13-B-only GPIO alternatives; full U13-A/U13-C data is required.
Required Before Schematic Wiring
- Complete CM5 pinout for U13-A, U13-B, U13-C.
- Exact B2B connector MPNs and footprints.
- Confirmation whether dual Ethernet MACs are exposed on the CM5 connectors.
- Confirmation whether enough same-voltage GPIO exists for the 32-bit deterministic bus.
- Final power tree decision for CM5
VCC_SYSIN: 4 V recommended vs 5 V system input and5V_HDMIhandling.
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