Sovereign Edge Aggregator PCB Design


I’ll lock the Tier-3 production baseline to Toradex Verdin iMX95 and update the architecture/design/checklist files so the review gates reference that module specifically.
Updated the production baseline to Toradex Verdin iMX95 across:
The checklist now requires Verdin-specific gates: exact Verdin iMX95 SKU, Toradex datasheet/carrier guide, Verdin connector footprint and mechanical model, Toradex power requirements, thermal guidance, and confirmation of Ethernet/PTP, TPM, Wi-Fi/BT, and NVMe implementation before schematic capture.
Create a Verdin iMX95 bring-up and procurement checklist from the updated gates.
I’ll create a Verdin iMX95 bring-up and procurement checklist from the updated gates, covering documents to obtain, parts to order, first-power validation, secure boot, Ethernet/PTP, NVMe, thermal, and sealed-node tests.
It covers procurement, Toradex documentation gates, carrier-side part selection, pre-schematic release criteria, first-article power-up, BSP boot, TPM/ATECC security validation, NVMe, Ethernet/PTP, wireless, thermal testing, and production-lock checks. Critical next gate: select the exact Toradex Verdin iMX95 SKU before schematic capture.
Select Verdin SKU
Research Toradex docs
Create power budget
Plan carrier schematic
Fix wrong component

Verdin iMX95 Bring-Up and Procurement Checklist
Purpose
This checklist converts the approved EcoSynQ Tier-3 production gates into an actionable procurement, design-input, and first-article bring-up plan for a sealed Toradex Verdin iMX95-based Witness Node.
This is a pre-schematic and first-article checklist. Exact voltages, current limits, pin names, and pass/fail thresholds must be finalized after the exact Verdin iMX95 SKU, carrier schematic, and Toradex design files are available.
Baseline Decision
  • Production module: Toradex Verdin iMX95
  • Product: EcoSynQ Tier-3 Witness Node
  • Architecture: sealed Verdin carrier, no exposed GPIO/debug, no SD card, passive cooling
  • Security: TPM 2.0 primary attestation, ATECC608B auxiliary identity/key element
  • Storage: NVMe ledger storage, eMMC/UFS only if provided by selected module/SKU
  • Networking: deterministic dual Ethernet with PTP/TSN validation
  • Power: USB-C PD input, 15 W minimum input capability, 12 W sustained system target
1. Procurement Package Checklist
1.1 Toradex Module and Development Hardware

Table


ItemRequired ActionAcceptance CriteriaStatus
Verdin iMX95 SKUSelect exact RAM, eMMC, Wi-Fi/BT, TPM, temperature grade, and lifecycle optionSKU documented with ordering code and lifecycle availability[ ]
Evaluation carrierOrder Toradex Verdin development/evaluation carrier compatible with iMX95Carrier supports initial power, Ethernet, debug, storage, and BSP validation[ ]
Production modulesOrder at least 3-5 Verdin iMX95 modules for prototype rotationSame SKU as production target unless explicitly marked EVT-only[ ]
Thermal accessoriesOrder heatsink/TIM or Toradex-recommended thermal hardwareCompatible with Verdin iMX95 thermal path[ ]
Debug/programming accessoriesOrder approved Toradex debug adapters/cablesSupports initial BSP bring-up without exposing debug on production enclosure[ ]
1.2 Required Vendor Documentation

Table


DocumentSourceRequired BeforeAcceptance CriteriaStatus
Verdin iMX95 datasheetToradexSchematicExact SKU electrical/mechanical limits documented[ ]
Verdin family carrier board design guideToradexSchematicPower, connector, layout, and interface rules available[ ]
Verdin iMX95 pinoutToradexSchematicAll used interfaces mapped to connector pins[ ]
Connector footprint and 3D modelToradex/vendorLayoutFootprint and keepouts verified against mechanical model[ ]
Reference carrier schematic/layoutToradexSchematic/layoutPower and interface implementation reviewed[ ]
Torizon/Linux BSP docsToradexFirmware bring-upBoot flow and image build path documented[ ]
Secure boot/provisioning docsToradex/NXPSecurity designFuse, key, update, and recovery flow documented[ ]
Thermal design guideToradexMechanical designThermal limits and heatsink interface defined[ ]
Lifecycle/PCN documentationToradexProcurement releaseLifecycle and notification path documented[ ]
1.3 Carrier-Side Parts to Select

Table


FunctionPreferred Production ApproachSelection GateStatus
USB-C PD sinkDedicated PD controller for 9 V/12 V profilesMust support 15 W minimum and safe fallback[ ]
Input protectionESD, overvoltage, reverse/backfeed protection as requiredSized from final power budget[ ]
Main carrier bucksHigh-efficiency bucks for 5 V/3.3 V/1.8 V as requiredNo LDO for high-current rails without thermal proof[ ]
TPM 2.0Primary measured-boot attestation device if not module-integratedLinux/Torizon support confirmed[ ]
ATECC608BAuxiliary identity/key deviceI2C address, secure provisioning flow defined[ ]
NVMe connectorM.2 Key M 2230/2242 targetThermal pad to chassis planned[ ]
Ethernet PHY/magneticsBased on Verdin-exposed Ethernet interfaces1000BASE-T RJ45 or 1000BASE-T1 decision made[ ]
WirelessUse Verdin integrated Wi-Fi/BT option if selected, otherwise certified moduleCertification path and antenna layout defined[ ]
Tamper sensorsHall/enclosure-open switch, optional meshEvents readable by secure software path[ ]
Test pointsHidden/pogo-only production accessNo exposed debug/GPIO on final enclosure[ ]
2. Pre-Schematic Design Gates

Table


GateRequirementPass CriteriaStatus
SKU lockExact Verdin iMX95 SKU selectedOrdering code and major features recorded[ ]
Power inputVerdin input voltage/current requirements knownCarrier power tree matches Toradex guide[ ]
Ethernet topologyDual Ethernet architecture chosenStandard RJ45 1000BASE-T or 1000BASE-T1 explicitly selected[ ]
PTP/TSNTiming path definedSelected Ethernet path supports LinuxPTP/IEEE 1588 requirements[ ]
NVMePCIe lane availability confirmedM.2 Key M mapping and reset/clkreq requirements known[ ]
SecurityTPM/ATECC roles assignedTPM primary, ATECC auxiliary, provisioning owner defined[ ]
Debug policyProduction debug access definedNo exposed JTAG/UART/GPIO; authenticated or disabled debug[ ]
WirelessIntegrated vs carrier-side wireless decidedCertification path and antenna keepout defined[ ]
StackupControlled-impedance stackup selected6-layer minimum, 8-layer preferred for dense high-speed carrier[ ]
ThermalPassive chassis concept definedThermal path from Verdin to aluminum chassis modeled[ ]
3. Procurement Release Gates
Do not release carrier PCB fabrication or long-lead procurement until these are complete:

Table


Release GateRequired EvidenceStatus
Toradex documentation package archivedDatasheet, carrier guide, pinout, mechanical, thermal, BSP, secure boot docs[ ]
Verdin connector selectedMPN, footprint, 3D model, mating height, keepouts[ ]
Stackup approvedFabricator stackup with impedance targets and coupons[ ]
Power budget completeRail-by-rail budget including Verdin, NVMe, Ethernet, wireless, TPM/ATECC[ ]
Thermal plan completeTIM, chassis, sensor locations, worst-case workload assumptions[ ]
Security plan completeKey provisioning, secure boot, measured boot, debug lock, recovery flow[ ]
Test plan completeBring-up sequence, test fixtures, pogo access, acceptance criteria[ ]
DFM review completeFabricator and assembler feedback resolved[ ]
4. First-Article Bring-Up Equipment

Table


EquipmentPurposeRequired
Current-limited bench supplySafe first power-onYes
USB-C PD analyzer/sourceVerify PD contract and current drawYes
Digital multimeterRail and continuity checksYes
Oscilloscope, 500 MHz+ preferredRails, reset, clocks, Ethernet timing checksYes
Thermal camera or thermocouplesPassive thermal validationYes
Ethernet PTP-capable test peerIEEE 1588/LinuxPTP validationYes
NVMe test SSDStorage bring-up and thermal/write validationYes
Toradex debug toolsEarly boot/debug before production lockEVT only
ESD-safe bench setupProtect module and carrierYes
5. First-Article Bring-Up Plan
5.1 Unpowered Inspection

Table


TestMethodPass CriteriaStatus
Visual inspectionMicroscope, compare against assembly drawingNo bridges, tombstones, missing parts, reversed polarized components[ ]
Connector inspectionInspect Verdin connector, M.2, USB-C, EthernetNo bent pins, solder void risk, contamination, or coplanarity issue[ ]
Rail-to-GND resistanceDMM ohms mode before module insertion if possibleNo hard shorts; resistance consistent across builds[ ]
Module seatingMechanical inspectionVerdin module fully seated, retention hardware installed[ ]
Enclosure clearanceDry fitNo interference with module, NVMe, antennas, thermal interface[ ]
5.2 Power-Up Sequence

Table


StepActionExpected ResultStatus
1Power carrier without Verdin if design permitsCarrier auxiliary rails valid; no overcurrent[ ]
2Power with Verdin installed using current-limited sourceCurrent below precomputed inrush/idle limit[ ]
3Verify USB-C PD contractCorrect 5 V/9 V/12 V profile negotiated[ ]
4Measure carrier railsRails within tolerance from final schematic[ ]
5Measure Verdin input railMatches Toradex requirement under idle and boot[ ]
6Check reset/power-good behaviorReset and enable timing follows Toradex guide[ ]
7Capture boot current profileNo unexpected brownout, oscillation, or thermal spike[ ]
5.3 Boot and BSP Validation

Table


TestMethodPass CriteriaStatus
Boot ROM/BSP bootBoot Toradex-supported image firstKernel reaches login or expected provisioning target[ ]
Device tree validationConfirm enabled carrier interfacesOnly required production interfaces enabled[ ]
Nonessential interface disableDisable unused display/GPIO/debug pathsNo external GPIO/debug exposure in production image[ ]
Torizon/Linux baseBuild and boot baseline imageRepeatable boot with recorded image hash[ ]
Recovery pathTest approved recovery/update mechanismDevice recoverable without exposing insecure debug[ ]
5.4 Security Bring-Up

Table


TestMethodPass CriteriaStatus
TPM detectLinux TPM toolsTPM present and usable for measured boot/attestation[ ]
ATECC608B detectI2C scan and CryptoAuthentication toolDevice present at expected address; provisioning state known[ ]
Secure boot dry runFollow Toradex/NXP flow in non-destructive mode firstKeys, images, and recovery process verified before fusing[ ]
Debug lock policyConfirm production settingsJTAG/UART disabled or authenticated for production[ ]
Tamper inputTrigger enclosure/hall sensorEvent recorded and sealed into local log[ ]
5.5 Storage Bring-Up

Table


TestMethodPass CriteriaStatus
NVMe detectlspci/nvme listSSD enumerates reliably across cold boots[ ]
NVMe thermalSustained write test with temperature loggingNo thermal shutdown; throttling behavior acceptable[ ]
Ledger filesystemCreate encrypted/append-only storage targetMounts reliably and survives power-cycle tests[ ]
Power-fail behaviorControlled power interruption during writesFilesystem and ledger recover cleanly[ ]
5.6 Ethernet and Timing Bring-Up

Table


TestMethodPass CriteriaStatus
Ethernet linkLink both ports to known-good peersStable link at intended rate[ ]
Throughputiperf3 or equivalentMeets target without excessive CPU or thermal load[ ]
PTP hardware timestampingethtool and linuxptp checksHardware timestamp path available and stable[ ]
PTP syncptp4l/phc2sys against referenceOffset/jitter meets product target after target is defined[ ]
Daisy-chain/mesh testUplink/downlink traffic scenarioNo packet loss under expected load[ ]
5.7 Wireless Bring-Up, If Populated

Table


TestMethodPass CriteriaStatus
Module detectlspci/lsusb/mmc depending interfaceWireless module enumerates[ ]
Wi-Fi scanRegulatory-domain-correct scanExpected networks visible[ ]
Bluetooth testController detect and advertise/scanBT operational if SKU requires it[ ]
RF coexistenceEthernet/NVMe/wireless simultaneous loadNo reset, thermal runaway, or unacceptable packet loss[ ]
Certification file checkConfirm module/regulatory dataRequired labels and antenna constraints documented[ ]
5.8 Thermal Validation

Table


TestMethodPass CriteriaStatus
Idle thermal soak30-60 minute idle in enclosureStable temperatures below component limits[ ]
CPU/NPU loadSustained workloadNo thermal shutdown; throttling within policy[ ]
NVMe write loadSustained writesSSD remains within rating or controlled throttling occurs[ ]
Ethernet loadDual-port throughput plus PTPPHY/magnetics area remains within safe limit[ ]
Combined worst caseCPU/NPU + NVMe + Ethernet + wireless if populatedSystem remains under thermal and power policy limits[ ]
6. Production Lock Checklist

Table


ItemRequirementStatus
Secure boot fused only after recovery validatedNo irreversible fuse step before recovery proof[ ]
Debug access policy approvedProduction units have no exposed unauthenticated debug[ ]
Power budget validatedMeasured current matches model with margin[ ]
Thermal model validatedMeasured thermal data matches enclosure model[ ]
PTP/TSN validatedTiming performance logged and repeatable[ ]
NVMe endurance policy validatedWrite amplification and thermal behavior acceptable[ ]
Manufacturing test fixture definedPogo pads, scripts, pass/fail thresholds complete[ ]
Serialization/provisioning definedDevice identity, certificates, keys, and labels tracked[ ]
Regulatory path definedWireless/EMC/security documentation plan exists[ ]
Field update/recovery validatedSigned OTA and local recovery tested[ ]
7. Open Decisions

Table


DecisionOptionsOwnerStatus
Exact Verdin iMX95 SKURAM/eMMC/Wi-Fi/TPM/temp grade variantsHardware[ ]
Ethernet physical layerDual RJ45 1000BASE-T vs 1000BASE-T1Hardware/System[ ]
TPM locationVerdin-integrated if available vs carrier-sideSecurity/Hardware[ ]
ATECC608B provisioningFactory provisioned vs in-house provisionedSecurity/Ops[ ]
NVMe size/form factor2230 vs 2242, 256 GB to 2 TBSystem/Ops[ ]
Wireless requirementVerdin Wi-Fi SKU vs no wireless vs carrier moduleProduct/Regulatory[ ]
Input power15 W USB-C PD only vs higher budgetHardware/Product[ ]
Enclosure85 mm x 56 mm class vs larger passive chassisMechanical[ ]
8. Pass/Fail Summary

Table


SectionResultNotes
Procurement package[ ] Pass / [ ] Fail
Pre-schematic gates[ ] Pass / [ ] Fail
Power-up[ ] Pass / [ ] Fail
BSP boot[ ] Pass / [ ] Fail
Security[ ] Pass / [ ] Fail
Storage[ ] Pass / [ ] Fail
Ethernet/PTP[ ] Pass / [ ] Fail
Wireless, if populated[ ] Pass / [ ] Fail
Thermal[ ] Pass / [ ] Fail
Production lock[ ] Pass / [ ] Fail
Board Status: [ ] Ready for schematic capture / [ ] Ready for EVT build / [ ] Ready for production lock / [ ] Requires rework
  • Purpose

  • Baseline Decision

  • 1. Procurement Package Checklist

  • 1.1 Toradex Module and Development Hardware

  • 1.2 Required Vendor Documentation

  • 1.3 Carrier-Side Parts to Select

  • 2. Pre-Schematic Design Gates

  • 3. Procurement Release Gates

  • 4. First-Article Bring-Up Equipment

  • 5. First-Article Bring-Up Plan

  • 5.1 Unpowered Inspection

  • 5.2 Power-Up Sequence

  • 5.3 Boot and BSP Validation

  • 5.4 Security Bring-Up

  • 5.5 Storage Bring-Up

  • 5.6 Ethernet and Timing Bring-Up

  • 5.7 Wireless Bring-Up, If Populated

  • 5.8 Thermal Validation

  • 6. Production Lock Checklist

  • 7. Open Decisions

  • 8. Pass/Fail Summary