Datasheet Pin Grouping


Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.
I’ll assign terminal order/orientation by the current generalized pin groups, with Power at order 1/top and Ground at order 10/bottom, then verify the properties.
Assigned Terminal Order and Pin Orientation across all pins and verified the updates.
Open items:
  • There are more groups than available non-power/non-ground side orientations, so Left/Right orientations are necessarily reused across groups.
Suggested next steps:
  1. Review the symbol rendering to confirm the layout reads well.
  2. If you want, I can rebalance individual pins within Address/Data/Control for a cleaner visual symbol.
Rebalance, review and update
Rebalance symbol visually
Fix metadata notes
Run review checks
Update review report

Part Review - W9825G6KH-5I
Date: 2026-07-13
Scope
Reviewed available part information, datasheet source, schematic terminal properties, footprint pads, and pin function grouping for Winbond W9825G6KH-5I.
Sources
The part already had a Datasheet URL property set, so it was not overwritten. The official Winbond URL appears to refer to the same W9825G6KH family datasheet and includes W9825G6KH-5I.
Available Part Metadata

Table


FieldProject valueDatasheet cross-check
Manufacturer Part NumberW9825G6KH-5IMatches
ManufacturerWinbondMatches
DescriptionSDRAM Memory IC 256Mbit Parallel 200 MHz 5 ns 54-TSOP II / expanded SDRAM descriptionMatches
Package or Case CodeTSOPPart is specifically TSOP II 54-pin, 400 mil, 0.80 mm pitch
Pin / pad count54Matches
Designator PrefixICAppropriate
Part TypeIntegrated CircuitsAcceptable but less specific than SDRAM/DRAM memory
Key Datasheet Specs
  • Memory type: high-speed synchronous DRAM (SDRAM)
  • Density / organization: 256 Mbit, 4M words x 4 banks x 16 bits
  • Interface: LVTTL
  • Supply: VDD and VDDQ 3.0 V to 3.6 V, nominal 3.3 V
  • Speed grade for -5I: 200 MHz CL3 or 133 MHz CL2
  • Operating temperature for -5I: -40 C to +85 C
  • Refresh: 8K cycles / 64 ms over -40 C to +85 C
  • Package: TSOP Type II, 54 leads, 400 mil, 0.80 mm pitch, RoHS/lead-free
Pin Function Groups Applied
Each physical pin is assigned to exactly one Pin Group.

Table


Pin GroupPinsDatasheet function
Core Power1 VDD_1, 14 VDD_2, 27 VDD_3VDD power for input buffers and internal logic
I/O Power3 VDDQ_1, 9 VDDQ_2, 43 VDDQ_3, 49 VDDQ_4VDDQ separated I/O buffer power
Core Ground28 VSS_1, 41 VSS_2, 54 VSS_3VSS ground for input buffers and internal logic
I/O Ground6 VSSQ_1, 12 VSSQ_2, 46 VSSQ_3, 52 VSSQ_4VSSQ separated I/O buffer ground
Address23 A0, 24 A1, 25 A2, 26 A3, 29 A4, 30 A5, 31 A6, 32 A7, 33 A8, 34 A9, 22 A10/AP, 35 A11, 36 A12Address inputs; A10 also auto-precharge control
Bank Select20 BS0, 21 BS1Bank selection inputs
Data I/O2 DQ0, 4 DQ1, 5 DQ2, 7 DQ3, 8 DQ4, 10 DQ5, 11 DQ6, 13 DQ7, 42 DQ8, 44 DQ9, 45 DQ10, 47 DQ11, 48 DQ12, 50 DQ13, 51 DQ14, 53 DQ15Bidirectional data bus
Data Mask15 LDQM, 39 UDQMLower/upper byte data mask inputs
Clock38 CLKSystem clock input
Clock Enable37 CKEClock enable / power-down and self-refresh control
Command/Control19 ~CS, 18 ~RAS, 17 ~CAS, 16 ~WESDRAM command inputs
No Connect40 NCLeave unconnected
Schematic Symbol Cross-Check
  • All 54 terminal pin numbers and names match the datasheet pin assignment.
  • Active-low command pins are represented with tilde names (~CS, ~RAS, ~CAS, ~WE), which correctly indicate the active-low functions named CS, RAS, CAS, and WE in the datasheet.
  • Pin types were updated from Unspecified to datasheet-backed values: Power In, Ground, Input, Bi-Directional, and Not Connected.
  • Pin descriptions were added from datasheet function descriptions.
Footprint Cross-Check
  • Footprint asset: SOP80P1176X120-54N.kicad_mod
  • Pad count: 54, matching the datasheet.
  • Pad pitch: 0.80 mm, matching the datasheet.
  • Fab outline in footprint: about 10.16 mm x 22.22 mm, matching nominal E1 x D body dimensions.
  • Overall footprint naming indicates 11.76 mm package width and 1.20 mm max height, matching the datasheet package outline.
  • Footprint has rectangular SMD pads, two rows, and pin-1 chamfer/marking, consistent with TSOP-II orientation.
Mismatches / Notes
  • No pinout mismatches found.
  • No pad-count or pitch mismatch found.
  • Metadata note: Package or Case Code is only TSOP; the datasheet-specific package is TSOP II 54-pin, 400 mil, 0.80 mm pitch. Consider updating metadata to be more specific.
  • Metadata note: Part Type is Integrated Circuits; DRAM or SDRAM Memory would be more specific if available.
  • Datasheet URL note: an official Winbond URL was found, but the existing Datasheet URL property already points to a PDF copy, so it was left unchanged per instruction.
  • Scope

  • Sources

  • Available Part Metadata

  • Key Datasheet Specs

  • Pin Function Groups Applied

  • Schematic Symbol Cross-Check

  • Footprint Cross-Check

  • Mismatches / Notes