Datasheet Pin Grouping

flux

Updated all pins to use more general functional groups, and set each pin’s Section property to the same value as its Pin Group.
Open items:
  • None.
Suggested next steps:
  1. Run/publish the component review checks.
  2. Update the report file if you want the new generalized grouping reflected there too.
A

adrian95

Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.

flux

I’ll assign terminal order/orientation by the current generalized pin groups, with Power at order 1/top and Ground at order 10/bottom, then verify the properties.

flux

Assigned Terminal Order and Pin Orientation across all pins and verified the updates.
Open items:
  • There are more groups than available non-power/non-ground side orientations, so Left/Right orientations are necessarily reused across groups.
Suggested next steps:
  1. Review the symbol rendering to confirm the layout reads well.
  2. If you want, I can rebalance individual pins within Address/Data/Control for a cleaner visual symbol.
Rebalance, review and update
Rebalance symbol visually
Fix metadata notes
Run review checks
Update review report
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Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
VDD_1
1
Power In
Power
Power
Top
1
VDD core power for input buffers and internal logic circuit inside DRAM.
DQ0
2
Bi-Directional
Data Bus
Data Bus
Right
5
Data input/output pin; multiplexed for data output and input.
VDDQ_1
3
Power In
Power
Power
Top
1
VDDQ separated I/O buffer power supply to improve DQ noise immunity.
DQ1
4
Bi-Directional
Data Bus
Data Bus
Right
5
Data input/output pin; multiplexed for data output and input.
DQ2
5
Bi-Directional
Data Bus
Data Bus
Right
5
Data input/output pin; multiplexed for data output and input.
VSSQ_1
6
Ground
Ground
Ground
Bottom
10
VSSQ separated I/O buffer ground to improve DQ noise immunity.
DQ3
7
Bi-Directional
Data Bus
Data Bus
Right
5
Data input/output pin; multiplexed for data output and input.
DQ4
8
Bi-Directional
Data Bus
Data Bus
Right
5
Data input/output pin; multiplexed for data output and input.
VDDQ_2
9
Power In
Power
Power
Top
1
VDDQ separated I/O buffer power supply to improve DQ noise immunity.
DQ5
10
Bi-Directional
Data Bus
Data Bus
Right
5
Data input/output pin; multiplexed for data output and input.
DQ6
11
Bi-Directional
Data Bus
Data Bus
Right
5
Data input/output pin; multiplexed for data output and input.
VSSQ_2
12
Ground
Ground
Ground
Bottom
10
VSSQ separated I/O buffer ground to improve DQ noise immunity.
DQ7
13
Bi-Directional
Data Bus
Data Bus
Right
5
Data input/output pin; multiplexed for data output and input.
VDD_2
14
Power In
Power
Power
Top
1
VDD core power for input buffers and internal logic circuit inside DRAM.
LDQM
15
Input
Data Bus
Data Bus
Right
5
Lower byte data mask; high masks lower data during write and places output buffer Hi-Z during read after latency.
~WE
16
Input
Control Bus
Control Bus
Left
7
Active-low write enable command input; sampled with RAS and CAS at CLK rising edge.
~CAS
17
Input
Control Bus
Control Bus
Left
7
Active-low column address strobe command input; sampled with RAS and WE at CLK rising edge.
~RAS
18
Input
Control Bus
Control Bus
Left
7
Active-low row address strobe command input; sampled with CAS and WE at CLK rising edge.
~CS
19
Input
Control Bus
Control Bus
Left
7
Active-low chip select; enables/disables command decoder.
BS0
20
Input
Address Bus
Address Bus
Left
3
Bank select input; selects bank during row/address latch time for activate/read/write.
BS1
21
Input
Address Bus
Address Bus
Left
3
Bank select input; selects bank during row/address latch time for activate/read/write.
A10/AP
22
Input
Address Bus
Address Bus
Left
3
Address input A10 / auto-precharge control; sampled during precharge to determine all-bank or selected-bank precharge.
A0
23
Input
Address Bus
Address Bus
Left
3
Address input; A0-A8 are multiplexed row/column address pins.

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