Pin Function Grouping

A

adrian95

Make section property as Pin Group

flux

Updated all pins so their Section property now matches their Pin Group.
A

adrian95

Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.

flux

I’ll assign section-level order with Power at 1 and Ground at 10, alternate the remaining groups between Left and Right, and preserve Top/Bottom for the supply pins. Since there are nine groups, order 9 will remain intentionally unused.

flux

Assigned and verified:
  • 1 Power — Top
  • 2 Internal Regulator — Left
  • 3 Reset — Right
  • 4 Clock — Left
  • 5 Port A — Right
  • 6 Port B — Left
  • 7 Port C — Right
  • 8 Port D — Left
  • 9 — unused
  • 10 Ground — Bottom
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Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
UART1_CK/TIM2_CH1/BEEP/(HS)PD4
1
Unspecified
Port D
Port D
Left
UART1_TX/AIN5/(HS)_PD5
2
Unspecified
Port D
Port D
Left
UART1_RX/AIN6/(HS)_PD6
3
Unspecified
Port D
Port D
Left
NRST
4
Unspecified
Reset
Reset
Right
OSCIN/PA1
5
Unspecified
Clock
Clock
Left
OSCOUT/PA2
6
Unspecified
Clock
Clock
Left
VSS
7
Unspecified
Ground
Ground
Bottom
VCAP
8
Unspecified
Internal Regulator
Internal Regulator
Left
VDD
9
Unspecified
Power
Power
Top
[SPI_NSS]_TIM2_CH3/(HS)_PA3
10
Unspecified
Port A
Port A
Right
PB5(T)/I2C_SDA_[TIM1_BKIN]
11
Unspecified
Port B
Port B
Left
PB4(T)/I2C_SCL_[ADC_ETR]
12
Unspecified
Port B
Port B
Left
PC3(HS)/TIM1_CH3_[TLI]_[TIM1_CH1N]
13
Unspecified
Port C
Port C
Right
PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
14
Unspecified
Port C
Port C
Right
PC5_(HS)/SPI_SCK_[TIM2_CH1]
15
Unspecified
Port C
Port C
Right
PC6(HS)/SPI_MOSI_[TIM1_CH1]
16
Unspecified
Port C
Port C
Right
PC7(HS)/SPI_MISO_[TIM1_CH2]
17
Unspecified
Port C
Port C
Right
PD1(HS)/SWIM
18
Unspecified
Port D
Port D
Left
PD2(HS)/AIN3/[TIM2_CH3]
19
Unspecified
Port D
Port D
Left
PD3_(HS)/AIN4/TIM2_CH2/ADC_ETR
20
Unspecified
Port D
Port D
Left

STM8S003F3P6TR