Part Audit Review

adrian95

adrian95

Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.

flux

I’ll audit the part metadata, locate the official STM32G0B1CBT3 datasheet if needed, update its Datasheet property, then verify symbol pins and footprint geometry against the manufacturer documentation.
Created a project doc

Part Audit

View Document
Part Audit Scope
Audit of STM32G0B1CBT3 metadata, official datasheet, 48-pin schematic symbol, LQFP48 footprint, and terminal descriptions/types.
Authoritative source Correct identity and key specifications Metadata review Schematic symbol review Pin numbering and names
All 48 current terminal numbers and names match the official LQFP48 pinout:
1 PC13, 2 PC14-OSC32_IN, 3 PC15-OSC32_OUT, 4 VBAT, 5 VREF+, 6 VDD/VDDA, 7 VSS/VSSA, 8 PF0-OSC_IN, 9 PF1-OSC_OUT, `10 PF2-NR...

flux

Audit complete. The existing Datasheet URL is already the official ST document, and all 48 symbol pin names/numbers match; key issues are incorrect TO package metadata, incorrect Logic/AND classification, missing pin types/descriptions, and footprint pads longer than ST’s example.
Full findings: Part Audit. An internal part-quality report was also filed for review.
Correct part metadata
Match ST footprint
Review pad-length tradeoff
Create bring-up plan
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Files

Pins

Symbol

Layout

Preview

PA10
Pin Number
32
PB12
Pin Number
24
PA4
Pin Number
15
PB1
Pin Number
20
PC7
Pin Number
31
PA2
Pin Number
13
PB0
Pin Number
19
PB15
Pin Number
27
PA0
Pin Number
11
PB7
Pin Number
46
PF1-OSC_OUT
Pin Number
9
PB5
Pin Number
44
PD3
Pin Number
41
PA1
Pin Number
12
PA9
Pin Number
29
VBAT
Pin Number
4
PB4
Pin Number
43
PB11
Pin Number
23
PA13
Pin Number
35
PC15-OSC32_OUT
Pin Number
3
PA7
Pin Number
18
PB8
Pin Number
47
PB13
Pin Number
25
PA8
Pin Number
28
PB9
Pin Number
48
VREF+
Pin Number
5
PA6
Pin Number
17
PB6
Pin Number
45
PA14-BOOT0
Pin Number
36
PB2
Pin Number
21
PD1
Pin Number
39
PC6
Pin Number
30
PA5
Pin Number
16
PC13
Pin Number
1
PB14
Pin Number
26
PA11_[PA9]
Pin Number
33
PF2-NRST
Pin Number
10
PD2
Pin Number
40
PC14-OSC32_IN
Pin Number
2
PB3
Pin Number
42
VDD/VDDA
Pin Number
6
VSS/VSSA
Pin Number
7
PF0-OSC_IN
Pin Number
8
PA12_[PA10]
Pin Number
34
PA3
Pin Number
14
PD0
Pin Number
38
PA15
Pin Number
37
PB10
Pin Number
22
Part Audit
Scope
Audit of STM32G0B1CBT3 metadata, official datasheet, 48-pin schematic symbol, LQFP48 footprint, and terminal descriptions/types.
Authoritative source
Correct identity and key specifications

Table

ItemDatasheet value for STM32G0B1CBT3
DeviceMainstream 32-bit MCU, Arm Cortex-M0+
Maximum CPU clock64 MHz
Flash128 Kbytes (B ordering-code suffix)
SRAM128 Kbytes with hardware parity, or 144 Kbytes when parity bits are used as data
Main supply1.7 V to 3.6 V
Package48-pin LQFP, 7 x 7 mm body, 0.50 mm lead pitch, ST package code 5B
Temperature-40 C to +125 C ambient (3 suffix), up to +130 C junction
Analog12-bit ADC; two 12-bit DAC channels; three comparators
Communications3 I2C, 3 SPI / 2 I2S, 6 USART, 2 LPUART, USB 2.0 FS host/device, USB Type-C PD, 2 FDCAN, HDMI CEC
Metadata review

Table

FieldCurrent valueResult
MPNSTM32G0B1CBT3Correct
ManufacturerSTMicroelectronicsCorrect
Pin count48Correct
Datasheet URLOfficial ST DS13560 PDFCorrect; unchanged
DescriptionFamily-level text says “up to 512 Kbytes Flash”Misleading for this exact B device, which has 128 Kbytes Flash
Package or Case CodeTOIncorrect; should identify LQFP48, 7 x 7 mm, 0.5 mm pitch
Part typeIntegrated CircuitsBroad but acceptable
Part subtypeLogicIncorrect; this is a microcontroller
Logic functionANDIncorrect and unrelated
LifecycleNew Product / full productionConsistent with available source information
Schematic symbol review
Pin numbering and names
All 48 current terminal numbers and names match the official LQFP48 pinout:
1 PC13, 2 PC14-OSC32_IN, 3 PC15-OSC32_OUT, 4 VBAT, 5 VREF+, 6 VDD/VDDA, 7 VSS/VSSA, 8 PF0-OSC_IN, 9 PF1-OSC_OUT, 10 PF2-NRST, 11 PA0, 12 PA1, 13 PA2, 14 PA3, 15 PA4, 16 PA5, 17 PA6, 18 PA7, 19 PB0, 20 PB1, 21 PB2, 22 PB10, 23 PB11, 24 PB12, 25 PB13, 26 PB14, 27 PB15, 28 PA8, 29 PA9, 30 PC6, 31 PC7, 32 PA10, 33 PA11 [PA9], 34 PA12 [PA10], 35 PA13, 36 PA14-BOOT0, 37 PA15, 38 PD0, 39 PD1, 40 PD2, 41 PD3, 42 PB3, 43 PB4, 44 PB5, 45 PB6, 46 PB7, 47 PB8, 48 PB9.
Pin metadata
  • All 48 terminals currently have Pin Type: Unspecified.
  • No terminals have a populated Pin Description.
  • This is a significant library-quality deficiency: supply pins should be typed as supply/power, GPIO pins as bidirectional I/O, and NRST according to its reset/input behavior. Descriptions should capture the primary pin function and important dedicated functions.
  • Alternate-function lists are extensive; they do not need to be displayed in the symbol name, but the part should at least provide useful terminal descriptions and electrical types for ERC and discovery.
Footprint review
Correct aspects
  • 48 pads are present and numbered 1 through 48.
  • The pad sequence and pin-1 marker orientation are consistent with a top-view LQFP48.
  • Lead pitch is 0.50 mm.
  • Body/fabrication outline is 7 x 7 mm.
  • A STEP 3D model is attached.
Dimensional difference from ST footprint example

Table

DimensionCurrent footprintST example
Pad width0.30 mm0.30 mm
Pad length1.475 mm1.20 mm
Pad-center distance from package center4.238 mmapproximately 4.25 mm
Approx. inner pad span7.00 mm7.30 mm
Approx. outer pad span9.95 mm9.70 mm
The current pads are about 0.275 mm longer than the manufacturer example, extending roughly 0.15 mm farther inward and 0.125 mm farther outward per side. This may be an intentional IPC-style land-pattern choice and is not automatically unmanufacturable, but it does not match ST’s example footprint. It should be validated against the intended assembly process and solder-joint goals before release.
Flagged mismatches and severity
  1. High — package metadata: TO is wrong; the exact device is LQFP48, 7 x 7 mm, 0.50 mm pitch.
  2. High — classification metadata: subtype Logic and logic function AND are incorrect for an STM32 microcontroller.
  3. High — terminal metadata: all pin types are unspecified and all pin descriptions are absent, reducing ERC value and user clarity.
  4. Medium — exact-device description: “up to 512 Kbytes” is family-level wording; this MPN has 128 Kbytes Flash.
  5. Medium — land pattern variance: pad length and pad spans differ from the official ST example, although the pitch, count, body outline, and numbering are correct.
  6. Pass — symbol pinout: all 48 pin names and numbers match the official LQFP48 pinout.
  7. Pass — datasheet: the existing URL is official and current; no property update was necessary.
  • Change Package or Case Code from TO to a clear LQFP48 identifier such as LQFP-48, 7x7 mm, 0.5 mm pitch.
  • Reclassify the part as a microcontroller and remove the AND logic-function metadata.
  • Replace the family-level description with exact-device wording that states 128 Kbytes Flash.
  • Populate Pin Type and Pin Description for every terminal from the pin-assignment table.
  • Decide whether to retain the IPC-style 1.475 mm pads or align them to ST’s 1.20 mm example, documenting the land-pattern standard used.
  • Visually verify the attached STEP model’s seating, rotation, pin-1 orientation, and lead-to-pad alignment before publishing.
An internal part-quality report was filed for review.

  • Scope

  • Authoritative source

  • Correct identity and key specifications

  • Metadata review

  • Schematic symbol review

  • Pin numbering and names

  • Pin metadata

  • Footprint review

  • Correct aspects

  • Dimensional difference from ST footprint example

  • Flagged mismatches and severity

  • Recommended corrections