MIMXRT1024 Pin Grouping
Reorganize all 144 terminals in the MIMXRT1024DAG5A part project into exactly 10 broad/general functional groups, with each physical pin assigned once only. Use this group-level layout scheme unless the persisted datasheet mapping proves a pin belongs elsewhere: 1 Power / Top; 2 EMC GPIO / Left; 3 SD GPIO / Right; 4 AD GPIO / Left; 5 Analog / Right; 6 USB / Left; 7 Clock / Right; 8 System Control / Left; 9 No Connect / Right; 10 Ground / Bottom. 'EMC GPIO' covers GPIO_EMC_* pins, 'SD GPIO' covers GPIO_SD_* pins, 'AD GPIO' covers GPIO_AD_* pins. Power covers all supply, regulator and power-domain pins except ground. Ground covers VSS_*, DCDC_GND and NGND_KEL0. System Control covers POR_B, TEST_MODE, WAKEUP, PMIC_ON_REQ, PMIC_STBY_REQ, ONOFF. Analog covers GPANAIO. USB covers four dedicated USB_OTG1 pins. Clock covers XTALI/XTALO and RTC_XTALI/RTC_XTALO. NC pins go to No Connect. For every terminal set Pin Group to the group name, Section to exactly the same value, Terminal Order to the group-level number 1 through 10 specified above, and Pin Orientation to the specified group orientation. Preserve pin name/number/type/description/footprint mapping and do not set sub-symbol suffixes. Inspect first, mutate in safe batches, then verify all 144: no missing Pin Group/Section/Order/Orientation, Section==Pin Group everywhere, group counts total 144, no duplicated/missing physical pin numbers, and every group has exactly the requested order/orientation. Return group counts and verification evidence.
Worked for 4 mins 33 sec
Completed all 144 terminals: Power 24; EMC GPIO 42; SD GPIO 19; AD GPIO 26; Analog 1; USB 4; Clock 4; System Control 6; No Connect 8; Ground 10. Exhaustive 3-page inspection verified 144/144 terminals, physical pin numbers 1–144 exactly once, no missing grouping properties, Section=Pin Group throughout, and every group has the requested order/orientation; no sub-symbol suffixes were set.
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MIMXRT1024DAG5A Part Audit
Scope and status
- Metadata/properties: Completed.
- Official documentation cross-check: Completed against NXP
IMXRT1024CEC, Rev. 2 (01/2022). - All 144 symbol terminals: Completed for number/name coverage and metadata completeness.
- PCB footprint identity, pad count, mapping, and geometry: Completed using structured layout inspection.
- Datasheet mutation: Unattempted / not required because the Datasheet URL was already populated with the authoritative NXP URL. No project property was changed.
Official sources
- NXP official datasheet: https://www.nxp.com/docs/en/data-sheet/IMXRT1024CEC.pdf
- NXP i.MX RT1024 family/product documentation landing page: https://www.nxp.com/IMXRT1024
The persisted part property was read as
Datasheet URL = https://www.nxp.com/docs/en/data-sheet/IMXRT1024CEC.pdf. The same URL is attached to the published Flux library record for this project, so no update was necessary.Inspected part metadata
Table
| Property | Current value | Audit result |
|---|---|---|
| Project/part name | MIMXRT1024DAG5A | Exact orderable MPN identity |
| Manufacturer Part Number | MIMXRT1024DAG5A | Matches NXP Table 2 |
| Manufacturer Name | NXP | Matches official manufacturer |
| Description | SOC ARM Cortex M7 Tray | Broadly correct but very terse; “Tray” is ordering/packing context rather than a functional description |
| Designator Prefix | IC | Appropriate |
| Part Type | Empty | Metadata omission; not mutated |
| Datasheet URL | https://www.nxp.com/docs/en/data-sheet/IMXRT1024CEC.pdf | Present and authoritative |
| Terminal count | 144 | Matches official package |
| Package/case property | No explicit Package or Case Code property found | Metadata omission; official package code is AG |
| BOM | No placed BOM item (expected for a part project) | Informational |
Exact orderable identity and package
NXP Table 2 explicitly lists MIMXRT1024DAG5A. Part-number nomenclature decodes:
M: mass productionIMXRT1024: i.MX RT1024 family with 4 MB flash SiP featureD: consumer junction-temperature gradeAG: 144-pin LQFP, 20 × 20 mm body, 0.5 mm pitch5: 500 MHzA: A0 silicon revision
Official package: plastic 144-pin LQFP, 20 × 20 mm body, 0.5 mm pitch. No exposed or thermal pad is specified; the package has exactly 144 perimeter leads.
Concise key specifications
- Arm Cortex-M7, up to 500 MHz, 16 KB instruction cache, 16 KB data cache, FPU, MPU and CoreSight debug.
- 4 MB on-chip flash, 256 KB configurable on-chip RAM/TCM, 96 KB boot ROM.
- Consumer grade: Tj 0 °C to +95 °C.
- Main operating supplies include DCDC_IN 3.0–3.6 V; VDD_HIGH_IN 3.0–3.6 V; VDD_SNVS_IN 2.40–3.6 V; NVCC_GPIO 3.0–3.6 V; NVCC_SD0 1.65–3.6 V; VDDA_ADC_3P3 3.0–3.6 V; USB VBUS 4.40–5.5 V. Core rail requirements depend on clock/power mode.
- Interfaces/peripherals: 10/100 Ethernet with IEEE 1588, USB 2.0 OTG with PHY, 2× uSDHC (SD/eMMC), 2× FlexCAN, 8× UART, 4× I²C, 4× SPI, 3× SAI, SPDIF, FlexIO, timers, 2× FlexPWM, 2× ADC, 4× analog comparators, and 90 GPIOs in this package.
- External memory support includes SDRAM, NAND, parallel NOR, SD/eMMC, and Quad SPI flash.
Schematic symbol audit
Verified matches
- Exactly 144 terminal components exist.
- Pin Number values are unique and cover 1 through 144 with no gaps, duplicates, or out-of-range values.
- Terminal names and numbers match NXP Tables 81 and 82. No name/number mismatch was found.
- Repeated rails are disambiguated with suffixes in the project (for example
VDD_SOC_IN_1andVSS_1), while preserving their correct physical pin numbers. - The eight NC pins are present at pins 77, 87, 88, 89, 90, 91, 92, and 104.
- Supply mapping matches the datasheet, including DCDC pins 34–38, SNVS/control pins 49–58, USB/clock pins 59–69, analog/reference pins 71–73, all VDD_SOC_IN pins, all VSS pins, and NVCC rails.
Concrete symbol metadata mismatches
Severity: High for library quality / ERC usefulness; not a physical pin-map error.
All 144 terminals have
Pin Type = Unspecified. No terminal has a populated Pin Description, Pin Group, or Section property. Consequently:- GPIO, power, ground, input, output, oscillator, USB analog, and NC pins are not electrically typed.
- Datasheet pin descriptions/default functions are absent.
- Functional/power grouping is absent.
- ERC and symbol readability cannot benefit from correct pin semantics.
No terminals are omitted or duplicated, but the symbol is semantically under-described.
PCB footprint audit
Identity and count
- Footprint asset:
QFP50P2200X2200X160-144N.kicad_mod. - Asset name encodes 0.50 mm pitch, approximately 22 × 22 mm lead-tip span, 1.60 mm height, and 144 leads. This identity is consistent with an AG-package 20 × 20 mm-body LQFP.
- Structured layout summary reports 144 pads and one footprint.
- No center exposed/thermal pad exists, matching the official package.
- A 3D model
MIMXRT1024DAG5A.stpis attached.
Pad mapping
The layout contains one pad corresponding to each of the 144 named terminals. Combined with the symbol’s complete unique 1–144 mapping, no missing or extra pad was found. The inspection surface exposes pads by terminal/signal designator rather than displaying their numeric pad-number field, so direct numeric pad-label persistence could not be independently displayed; however, count and one-to-one terminal presence are complete.
Critical geometry mismatch
Severity: Critical — footprint is unusable for fabrication as currently computed.
Although the footprint asset name identifies the correct package class, structured computed geometry is scaled approximately 1000× too small:
- Example pad centers appear around
x/y = ±0.010738 mmrather than approximately±10.7 mm. - Pad pitch is approximately
0.0005 mmfrom adjacent coordinates rather than 0.5 mm. - Computed pad size is approximately
0.0003 × 0.001475 mmrather than plausibly 0.30 × 1.475 mm.
This is a clear unit-scale/import error (meter/mm or 1000:1 scaling). If fabricated from the current computed footprint, the entire 144-pin land pattern would be microscopic and could not accept the 20 × 20 mm LQFP. The footprint package identity is correct, but its persisted computed geometry is critically incorrect.
Mismatch summary
Table
| Severity | Area | Concrete issue |
|---|---|---|
| Critical | PCB footprint | Entire land pattern is approximately 1000× too small: ~0.0005 mm pitch and ~0.0003 × 0.001475 mm pads instead of 0.5 mm pitch and mm-scale pads |
| High | Symbol metadata | All pins have Pin Type = Unspecified; all 144 lack Pin Description, Pin Group, and Section |
| Medium | Part metadata | Explicit Package/Case Code property is missing; official code is AG, 144-LQFP 20 × 20 mm, 0.5 mm pitch |
| Low | Part metadata | Part Type is empty and description is terse |
| Pass | MPN | Exact MIMXRT1024DAG5A identity matches NXP |
| Pass | Pin map | 144 unique pins, complete 1–144 coverage, no name/number mismatch |
| Pass | Pad count | 144 perimeter pads, no exposed pad |
| Pass | Datasheet | Official NXP Datasheet URL already present and persisted |
Mutation record
No mutation was made. The user requested only a Datasheet-property mutation if the property was missing. It was already present and authoritative, so changing it would have been unnecessary and outside the requested minimal-mutation scope. Symbol and footprint mismatches were intentionally left unchanged.
Scope and status
Official sources
Inspected part metadata
Exact orderable identity and package
Concise key specifications
Schematic symbol audit
Verified matches
Concrete symbol metadata mismatches
PCB footprint audit
Identity and count
Pad mapping
Critical geometry mismatch
Mismatch summary
Mutation record
