MIMXRT1024 Pin Grouping

adrian95

adrian95

flux

Reorganize all 144 terminals in the MIMXRT1024DAG5A part project into exactly 10 broad/general functional groups, with each physical pin assigned once only. Use this group-level layout scheme unless the persisted datasheet mapping proves a pin belongs elsewhere: 1 Power / Top; 2 EMC GPIO / Left; 3 SD GPIO / Right; 4 AD GPIO / Left; 5 Analog / Right; 6 USB / Left; 7 Clock / Right; 8 System Control / Left; 9 No Connect / Right; 10 Ground / Bottom. 'EMC GPIO' covers GPIO_EMC_* pins, 'SD GPIO' covers GPIO_SD_* pins, 'AD GPIO' covers GPIO_AD_* pins. Power covers all supply, regulator and power-domain pins except ground. Ground covers VSS_*, DCDC_GND and NGND_KEL0. System Control covers POR_B, TEST_MODE, WAKEUP, PMIC_ON_REQ, PMIC_STBY_REQ, ONOFF. Analog covers GPANAIO. USB covers four dedicated USB_OTG1 pins. Clock covers XTALI/XTALO and RTC_XTALI/RTC_XTALO. NC pins go to No Connect. For every terminal set Pin Group to the group name, Section to exactly the same value, Terminal Order to the group-level number 1 through 10 specified above, and Pin Orientation to the specified group orientation. Preserve pin name/number/type/description/footprint mapping and do not set sub-symbol suffixes. Inspect first, mutate in safe batches, then verify all 144: no missing Pin Group/Section/Order/Orientation, Section==Pin Group everywhere, group counts total 144, no duplicated/missing physical pin numbers, and every group has exactly the requested order/orientation. Return group counts and verification evidence.

flux

Completed all 144 terminals: Power 24; EMC GPIO 42; SD GPIO 19; AD GPIO 26; Analog 1; USB 4; Clock 4; System Control 6; No Connect 8; Ground 10. Exhaustive 3-page inspection verified 144/144 terminals, physical pin numbers 1–144 exactly once, no missing grouping properties, Section=Pin Group throughout, and every group has the requested order/orientation; no sub-symbol suffixes were set.
Review symbol and pinout
Inspect footprint mapping
Export pin table
Check symbol rendering
GPIO_EMC_12
Pin Number
3
GPIO_EMC_13
Pin Number
2
GPIO_EMC_14
Pin Number
1
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MIMXRT1024DAG5A

MIMXRT1024DAG5A thumbnail
High-Performance Arm® Cortex®-M7 Crossover MCU – 32-bit Arm Cortex-M7 crossover microcontroller for industrial automation, motor control, HMI, IoT gateways, audio processing, smart appliances, and real-time embedded systems. Operates at up to 500 MHz with 4 MB embedded Flash memory, 256 KB SRAM, and a 3.0 V to 3.6 V supply voltage. Features a single-precision FPU, DSP extensions, 19-channel 12-bit ADC, 10/100 Ethernet MAC, USB 2.0 High-Speed OTG with PHY, CAN FD, SD/MMC/eMMC, QuadSPI/HyperBus, FlexSPI, I²C, SPI, UART/USART, SAI, SPDIF, PWM timers, DMA, watchdog timers, TRNG, AES-128 hardware cryptography, and secure boot support for high-performance real-time applications. Designed for consumer and industrial embedded systems, it operates over a 0°C to +95°C junction temperature and is housed in a 144-pin LQFP (20 × 20 mm) package.
#NXP #MIMXRT1024DAG5A #iMXRT1024 #CortexM7 #Microcontroller #RealTimeMCU #Ethernet #CANFD #USBHS #MotorControl #IndustrialAutomation #EmbeddedSystems

Properties

MIMXRT1024DAG5A

NXP

Microprocessors

nxp.com/docs/en/data-sheet/IMXRT1024CEC.pdf

IC

parametric-v1

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