Part Datasheet Review


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MAX9526AEI+ Part Review

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Official datasheet already set: https://www.analog.com/media/en/technical-documentation/data-sheets/max9526.pdf Manufacturer: Analog Devices...
Completed the MAX9526AEI+ datasheet review and grouped every pin exactly once by primary function. The official Analog Devices datasheet was already set, pinout matched the 28-QSOP datasheet, and I updated pin groups, sections, pin types, orientations, and descriptions.
Open items:
  • Exact Maxim/ADI land pattern 90-0173 dimensions were not available in the extracted datasheet text, so the footprint was verified by package type, 28-pad count, and QSOP pitch rather than full dimensional QA.
Suggested next steps:
  1. Review the detailed findings in MAX9526AEI+ Part Review.
  2. If needed, provide the official land-pattern drawing for a stricter footprint audit.
  3. Next, I can update symbol placement visually so the grouped pins render cleanly by function.
  • Make the functional group more general.
  • Add a Section property to all pins, and apply the same value used in the Pin Group property to each pin's Section property.
Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.
I’ll generalize the pin groups, mirror each Pin Group into Section, then assign Terminal Order and orientations with Power at top/order 1 and Ground at bottom/order 10.
Updated all pins with more general functional groups and matched each pin’s Section to its Pin Group.
Open items:
  • Flux warned that “Reserved” is not a standard suggested Pin Group/Section value, but I kept it for the I.C. pin because that best reflects its datasheet role without incorrectly mixing it into another group.
Suggested next steps:
  1. Visually rearrange the symbol pins to reflect the new grouping/orientations.
  2. Run a final symbol/footprint QA pass before publishing the part.
Arrange and QA
Arrange symbol pins
Run final QA
Check Reserved pin
Update review document

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
VIN1
1
Input
Analog
Analog
Left
2
Single-ended composite video input 1; AC-couple input video with 0.1uF capacitor.
VREF
2
Passive
Analog
Analog
Left
2
Video reference bypass; bypass to AGND with 0.1uF capacitor as close as possible to the device.
VIN2
3
Input
Analog
Analog
Left
2
Single-ended composite video input 2; AC-couple input video with 0.1uF capacitor.
AGND
4
Ground
Ground
Ground
Bottom
10
Analog ground.
AVDD
5
Power In
Power
Power
Top
1
Analog power-supply input; connect to +1.8V and bypass to AGND with 0.1uF.
XTAL2
6
Input
Clock
Clock
Right
3
External crystal connection; connect to one terminal of crystal, or ground when applying external clock to XTAL/OSC.
XTAL/OSC
7
Input
Clock
Clock
Right
3
External crystal/oscillator input; connect to crystal terminal or external clock source.
I.C.
8
Reserved
Reserved
Reserved
Right
9
Internal connection; connect to DGND.
DEVADR
9
Input
Control
Control
Left
4
I2C device address select input; connect to DVDD, DGND, or SDA to select one of three slave addresses.
DVDD_1
10
Power In
Power
Power
Top
1
Digital power-supply input; connect to +1.8V and bypass to DGND with 0.1uF in parallel with 10uF.
DGND_1
11
Ground
Ground
Ground
Bottom
10
Digital ground; connect both DGND terminals together.
SDA
12
Bi-Directional
Control
Control
Left
4
I2C-compatible serial-data input/output; use 10k pullup to DVDDIO for full output swing.
SCL
13
Input
Control
Control
Left
4
I2C-compatible serial-clock input; use 10k pullup to DVDDIO for full output swing.
~IRQ
14
Output
Control
Control
Left
4
Hardware interrupt open-drain output; active low, use 10k pullup to DVDDIO for full output swing.
D0
15
Output
Data
Data
Right
5
Digital video output bit 0, LSB; configurable as sync output via Clock and Output register 0x0D.
D1
16
Output
Data
Data
Right
5
Digital video output bit 1; configurable as sync output via Clock and Output register 0x0D.
D2
17
Output
Data
Data
Right
5
Digital video output bit 2 for 10-bit ITU-R BT.656 4:2:2 output with embedded sync.
D3
18
Output
Data
Data
Right
5
Digital video output bit 3 for 10-bit ITU-R BT.656 4:2:2 output with embedded sync.
D4
19
Output
Data
Data
Right
5
Digital video output bit 4 for 10-bit ITU-R BT.656 4:2:2 output with embedded sync.
D5
20
Output
Data
Data
Right
5
Digital video output bit 5 for 10-bit ITU-R BT.656 4:2:2 output with embedded sync.
LLC
21
Output
Clock
Clock
Right
3
Line-locked 27MHz clock output; varies with horizontal line rate in line-locked mode.
DVDD_2
22
Power In
Power
Power
Top
1
Digital power-supply input; connect to +1.8V and bypass to DGND with 0.1uF in parallel with 10uF.
DGND_2
23
Ground
Ground
Ground
Bottom
10
Digital ground; connect both DGND terminals together.

MAX9526AEI+