Part Datasheet Review


Created a project doc

MAX9526AEI+ Part Review

View Document

Official datasheet already set: https://www.analog.com/media/en/technical-documentation/data-sheets/max9526.pdf Manufacturer: Analog Devices...
Completed the MAX9526AEI+ datasheet review and grouped every pin exactly once by primary function. The official Analog Devices datasheet was already set, pinout matched the 28-QSOP datasheet, and I updated pin groups, sections, pin types, orientations, and descriptions.
Open items:
  • Exact Maxim/ADI land pattern 90-0173 dimensions were not available in the extracted datasheet text, so the footprint was verified by package type, 28-pad count, and QSOP pitch rather than full dimensional QA.
Suggested next steps:
  1. Review the detailed findings in MAX9526AEI+ Part Review.
  2. If needed, provide the official land-pattern drawing for a stricter footprint audit.
  3. Next, I can update symbol placement visually so the grouped pins render cleanly by function.
  • Make the functional group more general.
  • Add a Section property to all pins, and apply the same value used in the Pin Group property to each pin's Section property.
Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.
I’ll generalize the pin groups, mirror each Pin Group into Section, then assign Terminal Order and orientations with Power at top/order 1 and Ground at bottom/order 10.
Updated all pins with more general functional groups and matched each pin’s Section to its Pin Group.
Open items:
  • Flux warned that “Reserved” is not a standard suggested Pin Group/Section value, but I kept it for the I.C. pin because that best reflects its datasheet role without incorrectly mixing it into another group.
Suggested next steps:
  1. Visually rearrange the symbol pins to reflect the new grouping/orientations.
  2. Run a final symbol/footprint QA pass before publishing the part.
Arrange and QA
Arrange symbol pins
Run final QA
Check Reserved pin
Update review document

D0
Pin Number
15
D2
Pin Number
17
VIN2
Pin Number
3
D5
Pin Number
20
XTAL2
Pin Number
6
D6
Pin Number
25
DGND_1
Pin Number
11
LLC
Pin Number
21
DEVADR
Pin Number
9
VREF
Pin Number
2
SDA
Pin Number
12
I.C.
Pin Number
8
D4
Pin Number
19
XTAL/OSC
Pin Number
7
SCL
Pin Number
13
VIN1
Pin Number
1
AVDD
Pin Number
5
DVDD_2
Pin Number
22
DVDDIO
Pin Number
24
D7
Pin Number
26
AGND
Pin Number
4
DGND_2
Pin Number
23
D1
Pin Number
16
D3
Pin Number
18
D9
Pin Number
28
DVDD_1
Pin Number
10
~IRQ
Pin Number
14
D8
Pin Number
27
Name
Pin #
Type
Part Type
Pin Description
Pin Group
VIN1
1
Input
Terminal
Single-ended composite video input 1; AC-couple input video with 0.1uF capacitor.
Analog
VREF
2
Passive
Terminal
Video reference bypass; bypass to AGND with 0.1uF capacitor as close as possible to the device.
Analog
VIN2
3
Input
Terminal
Single-ended composite video input 2; AC-couple input video with 0.1uF capacitor.
Analog
AGND
4
Ground
Terminal
Analog ground.
Ground
AVDD
5
Power In
Terminal
Analog power-supply input; connect to +1.8V and bypass to AGND with 0.1uF.
Power
XTAL2
6
Input
Terminal
External crystal connection; connect to one terminal of crystal, or ground when applying external clock to XTAL/OSC.
Clock
XTAL/OSC
7
Input
Terminal
External crystal/oscillator input; connect to crystal terminal or external clock source.
Clock
I.C.
8
Reserved
Terminal
Internal connection; connect to DGND.
Reserved
DEVADR
9
Input
Terminal
I2C device address select input; connect to DVDD, DGND, or SDA to select one of three slave addresses.
Control
DVDD_1
10
Power In
Terminal
Digital power-supply input; connect to +1.8V and bypass to DGND with 0.1uF in parallel with 10uF.
Power
DGND_1
11
Ground
Terminal
Digital ground; connect both DGND terminals together.
Ground
SDA
12
Bi-Directional
Terminal
I2C-compatible serial-data input/output; use 10k pullup to DVDDIO for full output swing.
Control
SCL
13
Input
Terminal
I2C-compatible serial-clock input; use 10k pullup to DVDDIO for full output swing.
Control
~IRQ
14
Output
Terminal
Hardware interrupt open-drain output; active low, use 10k pullup to DVDDIO for full output swing.
Control
D0
15
Output
Terminal
Digital video output bit 0, LSB; configurable as sync output via Clock and Output register 0x0D.
Data
D1
16
Output
Terminal
Digital video output bit 1; configurable as sync output via Clock and Output register 0x0D.
Data
D2
17
Output
Terminal
Digital video output bit 2 for 10-bit ITU-R BT.656 4:2:2 output with embedded sync.
Data
D3
18
Output
Terminal
Digital video output bit 3 for 10-bit ITU-R BT.656 4:2:2 output with embedded sync.
Data
D4
19
Output
Terminal
Digital video output bit 4 for 10-bit ITU-R BT.656 4:2:2 output with embedded sync.
Data
D5
20
Output
Terminal
Digital video output bit 5 for 10-bit ITU-R BT.656 4:2:2 output with embedded sync.
Data
LLC
21
Output
Terminal
Line-locked 27MHz clock output; varies with horizontal line rate in line-locked mode.
Clock
DVDD_2
22
Power In
Terminal
Digital power-supply input; connect to +1.8V and bypass to DGND with 0.1uF in parallel with 10uF.
Power
DGND_2
23
Ground
Terminal
Digital ground; connect both DGND terminals together.
Ground

MAX9526AEI+