Part Review and Datasheet Verification

flux

I’ll update the datasheet-backed pin metadata first, then rebuild the footprint as a proper 40-pin 600 mil PDIP and verify the result.

flux

Symbol pin metadata is updated; I’m now correcting the footprint scale/geometry to match the 40-pin 600 mil PDIP.

flux

Updated the dsPIC30F4013 part: added datasheet-backed pin descriptions, corrected pin types, added missing alternate-function labels, normalized AVSS, and rebuilt the footprint as a 40-pin 600 mil PDIP with 2.54 mm pitch, 15.24 mm row spacing, 1.6 mm through-hole pads, 0.8 mm drills, and a pin-1 marker.
Open items:
  • Flux did not apply the case-only rename from Vss to VSS on the duplicate ground pins, but their pin type, descriptions, numbers, and footprint pads are corrected.
Suggested next steps:
  1. Re-run the part review to confirm no remaining symbol/footprint mismatches.
  2. Publish the corrected component version.
  3. Optionally switch the Datasheet URL to the official Microchip PDF.
Review, publish, datasheet
Final part review
Publish component
Update datasheet URL
Check ERC DRC
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Files

Pins

Symbol

Layout

Preview

AN0/VREF+/CN2/RB0
Pin Number
2
AN5/IC8/CN7/RB5
Pin Number
7
AN1/VREF-/CN3/RB1
Pin Number
3
PGD/EMUD/AN7/RB7
Pin Number
9
AN4/IC7/CN6/RB4
Pin Number
6
AN3/CN5/RB3
Pin Number
5
PGC/EMUC/AN6/OCFA/RB6
Pin Number
8
AN2/SS1/LVDIN/CN4/RB2
Pin Number
4
Name
Pin #
Type
Part Type
Pin Description
Terminal Order
MCLR
1
Input
Terminal
Master Clear reset input or programming voltage input; active-low reset.
AN0/VREF+/CN2/RB0
2
Bi-Directional
Terminal
PORTB GPIO RB0; analog input AN0; positive ADC reference VREF+; change notification CN2.
AN1/VREF-/CN3/RB1
3
Bi-Directional
Terminal
PORTB GPIO RB1; analog input AN1; negative ADC reference VREF-; change notification CN3.
AN2/SS1/LVDIN/CN4/RB2
4
Bi-Directional
Terminal
PORTB GPIO RB2; analog input AN2; SPI1 slave select SS1; low-voltage detect input LVDIN; change notification CN4.
AN3/CN5/RB3
5
Bi-Directional
Terminal
PORTB GPIO RB3; analog input AN3; change notification CN5.
AN4/IC7/CN6/RB4
6
Bi-Directional
Terminal
PORTB GPIO RB4; analog input AN4; input capture IC7; change notification CN6.
AN5/IC8/CN7/RB5
7
Bi-Directional
Terminal
PORTB GPIO RB5; analog input AN5; input capture IC8; change notification CN7.
PGC/EMUC/AN6/OCFA/RB6
8
Bi-Directional
Terminal
PORTB GPIO RB6; analog input AN6; ICSP clock PGC; ICD clock EMUC; output compare fault input OCFA.
PGD/EMUD/AN7/RB7
9
Bi-Directional
Terminal
PORTB GPIO RB7; analog input AN7; ICSP data PGD; ICD data EMUD.
AN8/RB8
10
Bi-Directional
Terminal
PORTB GPIO RB8; analog input AN8.
VDD
11
Power In
Terminal
Positive supply for logic and I/O pins.
Vss
12
Ground
Terminal
Ground reference for logic and I/O pins.
OSC1/CLKI
13
Input
Terminal
Oscillator crystal input or external clock source input CLKI.
OSC2/CLKO/RC15
14
Bi-Directional
Terminal
Oscillator crystal output or CLKO; also PORTC GPIO RC15 depending on oscillator mode.
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
15
Bi-Directional
Terminal
PORTC GPIO RC13; ICD secondary data EMUD1; secondary oscillator input SOSCI; Timer2 clock T2CK; UART1 alternate TX U1ATX; change notification CN1.
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
16
Bi-Directional
Terminal
PORTC GPIO RC14; ICD secondary clock EMUC1; secondary oscillator output SOSCO; Timer1 clock T1CK; UART1 alternate RX U1ARX; change notification CN0.
INT0/RA11
17
Bi-Directional
Terminal
PORTA GPIO RA11; external interrupt input INT0.
IC2/INT2/RD9
18
Bi-Directional
Terminal
PORTD GPIO RD9; input capture IC2; external interrupt input INT2.

DSPIC30F4013-20I/P

DSPIC30F4013-20I/P thumbnail