Part Audit Review

A

adrian95

Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.

flux

I’ll audit the part metadata, locate the official Infineon datasheet if needed, update the Datasheet property, then verify the symbol pins and footprint against the manufacturer documentation.
Created a project doc

Part Audit Report

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Part Audit Report Scope and sources
Reviewed the published Flux part, its project properties, ten schematic terminals, imported KiCad footprint, and attached 3D model. Cross-checked against the official Infineon product page and official BSC059N04LS6 datasheet URL:
The part already had a Datasheet URL set (a Mouser-hosted copy), so it was not changed. The official Infineon URL above is preferred for future maintenance.
Current part metadata Key specifications

flux

Audit complete. The MPN, manufacturer, electrical ratings, and pins 1–8 are correct; the existing Datasheet URL was already populated, so it was not changed.
Key issues:
  • High: 10 schematic terminals versus 8 datasheet pins.
  • High: Full-area paste opening on the thermal/drain pad instead of segmented stencil apertures.
  • Missing pin descriptions and electrical types.
  • Inconsistent package designation.
Full findings: Part Audit Report. I also filed an internal part-quality report for the production-critical issues.
Fix symbol and stencil
Update datasheet source
Validate footprint geometry
Clean silkscreen labels
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Symbol

Layout

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Part Audit Report
Scope and sources
Reviewed the published Flux part, its project properties, ten schematic terminals, imported KiCad footprint, and attached 3D model. Cross-checked against the official Infineon product page and official BSC059N04LS6 datasheet URL:
The part already had a Datasheet URL set (a Mouser-hosted copy), so it was not changed. The official Infineon URL above is preferred for future maintenance.
Current part metadata

Table

FieldCurrent valueAssessment
Manufacturer Part NumberBSC059N04LS6ATMA1Correct ordering code
ManufacturerInfineonCorrect
Part TypeTransistors / MOSFETCorrect
MountSurface MountCorrect
Designator PrefixQCorrect
DescriptionN-channel 40 V; 17 A at ambient; 49/59 A case-rated; 3/38 W; PG-TDSON-8-6Electrical ratings broadly correct; package suffix is inconsistent with current Infineon naming
Datasheet URLMouser-hosted Infineon Rev. 2.00 PDFPresent; no update required by the request
Terminal count10Does not match the datasheet's eight numbered electrical pins
Footprint tagTDSON-8 FLConsistent with the datasheet's fused-lead/enlarged-source package family
3D modelBSC059N04LS6ATMA1.stpPresent; dimensional alignment was not independently measurable from the available model metadata
Key specifications
Values below were recovered from the official Infineon datasheet/product page. The PDF extraction did not return Flux inline citation IDs, so treat them as source-verified review data rather than citation-complete evidence.

Table

ParameterValue / condition
DeviceOptiMOS 6 N-channel power MOSFET, logic-level
Drain-source voltage40 V max
Gate-source voltage±20 V max
Continuous drain current59 A at VGS=10 V, TC=25 °C
Continuous drain current49 A at VGS=4.5 V, TC=25 °C
Ambient-limited drain current17 A at TA=25 °C, RthJA=50 °C/W
Pulsed drain current236 A max
RDS(on)4.7 mΩ typ, 5.9 mΩ max at VGS=10 V, ID=50 A
RDS(on)6.8 mΩ typ, 8.4 mΩ max at VGS=4.5 V, ID=50 A
Gate threshold1.3–2.3 V
Total gate charge9.4 nC typ at 10 V; 4.6 nC typ at 4.5 V
Input capacitance640 pF typ, 830 pF max
Power dissipation38 W at TC=25 °C; 3 W at TA=25 °C with stated PCB thermal condition
Junction temperature-55 to +175 °C
RthJC, bottom4 °C/W max
RthJA50 °C/W max using the datasheet's specified PCB copper area
Product statusActive and preferred
Datasheet pinout

Table

Datasheet pinRequired electrical functionCurrent terminal nameResult
1SourceS_1Functionally correct
2SourceS_2Functionally correct
3SourceS_3Functionally correct
4GateGCorrect
5DrainD_1Functionally correct
6DrainD_2Functionally correct
7DrainD_3Functionally correct
8DrainD_4Functionally correct
9No numbered datasheet pinD_5Extra library terminal; represents additional drain copper, not a separate device pin
10No numbered datasheet pinS_4Extra library terminal; represents enlarged source copper, not a separate device pin
Symbol findings
  1. Electrical pin count mismatch: The datasheet defines eight numbered pins. The Flux part exposes ten terminals by promoting two footprint copper regions to schematic terminals.
  2. Pin descriptions are missing: All ten terminals lack a Pin Description property.
  3. Pin types are unspecified: All terminals use Pin Type: Unspecified. Gate should be Input; source and drain terminals are normally Passive for ERC purposes.
  4. Extra-terminal naming is misleading: D_5 / pin 9 and S_4 / pin 10 imply real datasheet pins. If retained for copper mapping, they should be clearly described as internally connected exposed/enlarged copper and grouped with Drain or Source.
  5. Base pin functions 1–8 are correctly mapped.
Footprint findings
  1. Package family and body size are broadly aligned: The footprint is tagged TDSON-8 FL and uses a nominal 5 mm × 6 mm body outline, matching the SuperSO8 / PG-TDSON-8 fused-lead family.
  2. Base pads 1–8 map correctly: Pads 1–3 are source, pad 4 is gate, and pads 5–8 are drain.
  3. Additional copper decomposition is electrically plausible: Large pad 9 is mapped to drain and pad 10 to source, matching the package's drain thermal copper and enlarged source interconnection concept. These should not appear as separate numbered schematic pins.
  4. High-risk paste-mask mismatch: Pad 9 is a single 3.75 mm × 4.41 mm pad on F.Cu/F.Paste/F.Mask, producing one full-area paste opening. Infineon's recommended land pattern uses segmented stencil apertures over the large thermal region (approximately a 2 × 2 array). Full paste coverage can cause excessive solder volume, floating, tilt, and voiding.
  5. Footprint validation limitation: The PDF drawing was OCR-readable but did not provide a complete coordinate table. Exact pad-center and solder-mask geometry should be checked against Infineon's downloadable package CAD data before release.
  6. Silkscreen/reference text: Imported reference/value text is centered over the component and may overlap the body/pads in board usage; library presentation should be cleaned up.
Package-name mismatch
The project description says PG-TDSON-8-6. The official product page currently identifies the product as SuperSO8 5x6 / PG-TDSON-8, while the datasheet uses PG-TDSON-8 FL / TDSON-8 FL (enlarged source interconnection). A current Infineon material declaration also references PG-TDSON-8-25. These suffixes appear to be manufacturer package-revision identifiers; the part should use one authoritative package designation consistently rather than PG-TDSON-8-6 without supporting evidence.
Mismatches and severity

Table

SeverityFindingRecommended correction
HighFull-area paste opening on large drain/thermal pad instead of segmented aperturesRebuild F.Paste for the exposed pad from the official recommended stencil pattern
HighTen schematic terminals vs eight datasheet pinsKeep only pins 1–8 as user-facing terminals, or hide/group auxiliary copper pads so they are not separate schematic pins
MediumMissing pin descriptions and unspecified electrical typesAdd datasheet-derived descriptions and set Gate=Input, Source/Drain=Passive
MediumPackage naming inconsistent (PG-TDSON-8-6 vs official FL/current naming)Normalize description and Package or Case Code to the official designation used by the selected datasheet/CAD package
LowExtra copper terminals named as D_5/S_4Rename or document them as exposed/internal copper if the platform requires terminals for pad mapping
LowCentered silkscreen reference/value textMove reference outside the package body and keep value hidden on silkscreen
Overall assessment
The MPN, manufacturer, core electrical description, and numbered pin functions 1–8 are correct. The part should not be released for production without correcting or explicitly validating the exposed-pad paste pattern and resolving the ten-terminal versus eight-pin representation. The existing datasheet link is populated, but replacing it with the official Infineon URL would improve provenance even though the request only required an update when missing.

  • Scope and sources

  • Current part metadata

  • Key specifications

  • Datasheet pinout

  • Symbol findings

  • Footprint findings

  • Package-name mismatch

  • Mismatches and severity

  • Overall assessment