ASM1061 Pin Audit

Check this schematic component against the datasheet for [MPN] and assign the correct pin orientation, section, and terminal order without changing, replacing, renumbering, or remapping any pins. Remove the Pin Group property from all pins if it exists. Place Power pins first and Ground pins last. Within each section, distribute the pins as evenly as possible between the left and right sides; for example, split 10 pins as 5/5 and 11 pins as 5/6 or 6/5. If a section contains only one pin, leave it on the most appropriate side. Keep the symbol compact, balanced, and visually symmetrical. If a pin function is unclear, assign Unclear / Check datasheet, then apply all changes directly to the schematic component.

Thought for 11 sec

flux

I’ll apply this to the current ASM1061 part, preserving every pin number and mapping. I’ll organize pins into balanced functional sections, set orientation and terminal order, remove Pin Group everywhere, then verify the symbol metadata.

Worked for 2 mins 54 sec

Created a project doc

Part Audit

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Part Audit Scope

Audit of the ASM1061 part metadata, datasheet, schematic terminals, footprint mapping, and symbol organization.

Part metadata Key specifications

PCI Express Gen2 x1 upstream interface, supporting 2.5 and 5 GT/s signaling.
Two SATA PHY ports supporting 1.5, 3.0, and 6.0 Gb/s.
Supports IDE/AHCI mode, NCQ, port multiplier, SSC, ECRC, and Advanced Error Reporting.
External 20 MHz crystal and 100 MHz PCI Express reference clock.
Supports a 64 KB SPI flash for option ROM.
Integrated 3.3 V to 1.25 V switching regulator.
3.3 V rails: 3.0 to 3.6 V recommended.
1.25 V rails: 1.20 to 1.30 V recommended.
Operating junction temperature: 0 to 120 C; case temperature: 25 to 85 C.
PREXT and SREXT each require a 12.1 kOhm reference resistor to ground.

flux

Applied the ASM1061 symbol organization directly: all 49 pin mappings and numbers were preserved, Pin Group was removed, and balanced sections/orientations with unique terminal orders were assigned—Power first and Ground last.

Key findings and specifications are documented in Part Audit. Main flags: all pin types remain Unspecified, pin descriptions are missing, and exposed pad 49 is not explicitly defined in the QFN-48L datasheet.

Complete pin metadata

Resolve exposed pad

Audit footprint geometry

Improve part description

Files

Pins

Symbol

Layout

3D View

Part Audit

Scope

Audit of the ASM1061 part metadata, datasheet, schematic terminals, footprint mapping, and symbol organization.

Part metadata

Table

Field	Current value	Assessment
Manufacturer	ASMedia Technology Inc.	Matches datasheet
MPN	ASM1061	Matches datasheet
Description	PCI BUS CONTROLLER, CMOS	Too generic; datasheet identifies it as a PCI Express 2.0 x1 to dual-port SATA 6 Gb/s controller
Datasheet URL	Existing attached ASM1061 Data Sheet Rev. 1.8 PDF	Present; no URL update required
Datasheet revision	Rev. 1.8, April 16, 2012	Verified from attached PDF
Package	QFN-48L, 7 mm x 7 mm, 0.50 mm pitch, up to 0.90 mm height	Footprint naming is consistent
Schematic terminals / footprint pads	49	48 perimeter leads plus an exposed-pad entry

Key specifications

PCI Express Gen2 x1 upstream interface, supporting 2.5 and 5 GT/s signaling.
Two SATA PHY ports supporting 1.5, 3.0, and 6.0 Gb/s.
Supports IDE/AHCI mode, NCQ, port multiplier, SSC, ECRC, and Advanced Error Reporting.
External 20 MHz crystal and 100 MHz PCI Express reference clock.
Supports a 64 KB SPI flash for option ROM.
Integrated 3.3 V to 1.25 V switching regulator.
3.3 V rails: 3.0 to 3.6 V recommended.
1.25 V rails: 1.20 to 1.30 V recommended.
Operating junction temperature: 0 to 120 C; case temperature: 25 to 85 C.
PREXT and SREXT each require a 12.1 kOhm reference resistor to ground.

Pinout cross-check

Pins 1 through 48 match the datasheet pin numbers and functions. Duplicate supply and ground names use Flux-specific suffixes (_1, _2, etc.) but retain the correct physical pin numbers. Signal names for PCI Express, SATA, SPI, crystal, GPIO, reset, LED, and test mode match the datasheet.

The schematic-to-footprint name mapping is complete for all 49 current entries; no duplicate or missing mapped terminal names were found.

Symbol organization applied

All existing pin numbers, names, and footprint mappings were preserved. Pin Group was removed from every terminal. Unique terminal orders 1 through 49 were assigned with Power first and Ground last.

Table

Section	Pin count	Left / Right split
Power	15	7 / 8
PCI Express	7	4 / 3
SATA	8	4 / 4
Clock	2	1 / 1
SPI	4	2 / 2
GPIO and Control	5	3 / 2
Ground	8	4 / 4

Flagged mismatches and limitations

Pin descriptions are absent: all terminals lack the Pin Description property.
Pin electrical types are incomplete: all 49 terminals remain Unspecified, despite the datasheet defining input, output, bidirectional, power, ground, pull-up, pull-down, and differential roles.
Exposed-pad ambiguity: the datasheet calls the package QFN 48L and its pin table lists only pins 1-48. The current part adds EP as pin/pad 49. This is common footprint-library practice for an exposed thermal pad, but the attached datasheet does not explicitly assign it electrical pin number 49 or state its connection. Treat EP connectivity as Unclear / Check datasheet or package drawing before using it electrically.
Footprint geometry only partially verified: the footprint name is consistent with 7 mm x 7 mm, 0.50 mm pitch, 0.90 mm maximum height, and 49 numbered land entries. Exact perimeter land dimensions, exposed-pad land size, solder-mask/paste segmentation, and courtyard dimensions could not be independently read from the available indexed geometry.
Description is generic: PCI BUS CONTROLLER, CMOS should ideally be replaced with a specific functional description.
Visual rendering limitation: the project contains a custom symbol asset. Terminal Section, Pin Orientation, and Terminal Order metadata are now set, but the current custom asset may continue to control the rendered pin locations until the symbol is switched to a parametric style or the custom SVG is regenerated.

Recommended follow-up

Populate datasheet-derived Pin Description and Pin Type properties for all terminals.
Confirm the exposed-pad electrical connection from an authoritative package drawing, reference design, or manufacturer clarification.
Inspect the raw footprint land pattern against the QFN package dimensions and the intended assembly process.
Replace the generic description with: PCI Express Gen2 x1 to dual-port SATA 6 Gb/s controller.

Scope
Part metadata
Key specifications
Pinout cross-check
Symbol organization applied
Flagged mismatches and limitations
Recommended follow-up