Nice — you can do a clean pulse + latch using a single quad Schmitt-NAND chip: 74HC132 (or 74LVC132 for 3.3 V systems). The HC132 contains four 2-input NAND gates with Schmitt inputs so you can both clean a noisy SYN480R DATA line and build an SR latch (NAND SR is active-LOW) inside one package. Only a few passives and a driver transistor are needed.
Below is a ready-to-build recipe (parts, wiring, explanation, tuning tips, and an ASCII schematic) — no extra logic ICs required.
Parts (per latch)
1 × 74HC132 (quad 2-input NAND with Schmitt inputs).
If your system is 3.3 V use 74LVC132 / 74HC132 rated for 3.3 V.
Rin = 47 kΩ (input series)
Cfilter = 10 nF (input RC to ground) — tweak for debounce/clean time
Rpulldown = 100 kΩ (pull-down at input node, optional)
Rpullup = 100 kΩ (pull-up for active-LOW R input so reset is idle HIGH)
Rbase = 10 kΩ, Q = 2N2222 (NPN) or small N-MOSFET (2N7002) to drive your load
Diode for relay flyback (1N4001) if you drive a coil
Optional small cap 0.1 µF decoupling at VCC of IC
Concept / how it works (short)
Use Gate1 (G1) of 74HC132 as a Schmitt inverter by tying its two inputs together and feeding a small RC filter from SYN480R.DATA. This removes HF noise and provides a clean logic transition. Because it's a NAND with tied inputs its function becomes an inverter with Schmitt behavior.
Use G2 & G3 as the cross-coupled NAND pair forming an SR latch (active-LOW inputs S̄ and R̄).
A low on S̄ sets Q = HIGH.
A low on R̄ resets Q = LOW.
Wire the cleaned/inverted output of G1 to S̄. A valid received pulse (DATA high) produces a clean LOW on S̄ (because G1 inverts), setting the latch reliably even if the pulse is brief.
R̄ is your reset input (pushbutton, HT12D VT, MCU line, etc.) — idle pulled HIGH.
Q drives an NPN/MOSFET to switch your load (relay, LED, etc.).
Recommended wiring (pin mapping, assume one chip; use datasheet pin numbers)
I’ll refer to the 4 gates as G1, G2, G3, G4. Use G4 optionally for additional conditioning or to build a toggler later.
SYN480R.DATA --- Rin (47k) ---+--- Node A ---||--- Cfilter (10nF) --- GND
|
Rpulldown (100k) --- GND (optional, keeps node low)
Node A -> both inputs of G1 (tie inputs A and B of Gate1 together)
G1 output -> S̄ (S_bar) (input1 of Gate2)
Gate2 (G2): inputs = S̄ and Q̄ -> output = Q
Gate3 (G3): inputs = R̄ and Q -> output = Q̄
R̄ --- Rpullup (100k) --- VCC (reset is idle HIGH; pull low to reset)
(optional) R̄ can be wired to a reset pushbutton to GND or to an MCU pin
Q -> Rbase (10k) -> base of 2N2222 (emitter GND; collector to one side of relay coil)
Other side of relay coil -> +V (appropriate coil voltage)
Diode across coil
If you prefer MOSFET low side switching:
Q -> gate resistor 100Ω -> gate of 2N7002
2N7002 source -> GND ; drain -> relay coil low side
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