Access Reader Design
Access Reader — важная правка по РАЗМЕЩЕНИЮ разъёмов (ты на placement): ВСЕ разъёмы и клеммники ставь ПО КРАЮ платы, ориентированными наружу, с зазором под вставку кабеля/штекера. Сейчас RJ45 Ethernet стоит ПОСЕРЕДИНЕ — в него физически не воткнуть провод, перемести на кромку. На край разъёмной стороной наружу: RJ45 (Ethernet), клеммник входа 9–32В DC, клеммники 2 реле (NO/NC/COM), сервисный USB, клеммники/хедеры RS-485, Wiegand и 2 входов, разъём/шлейф GM861 (QR), 2-pin разъём катушки 125к (J101). Вход кабеля не должен перекрываться компонентами, крепёжными отверстиями или соседними разъёмами (проверь высоту/вылет коннектора наружу за контур). Зону поднесения карт (антенны 13.56/125к) держи свободным краем без разъёмов. Это правило — жёсткое: неудобный доступ к разъёму = брак. Обнови placement и manufacturing notes, отметь этот constraint в ready-to-export чеклисте.
Worked for 4 mins 30 sec
Created a project doc
Access Reader Factory Package Run — 2026-07-09
Full first Rev A prototype preserved: PoE AG9905-MTB, RJ45/W5500 Ethernet, 9-32 V DC LMR16020 branch and ESP32-S3 Wi-Fi are populated. Criti...
Сделал автономный проход и экспортировал артефакты; все ссылки на Gerber+drill, BOM, BOM с DNP-колонкой и Pick-and-Place собраны в Access Reader Factory Package Run — 2026-07-09.
Что не удалось: пакет не order-ready — routing не завершён, DRC всё ещё показывает много airwires; stackup tool принял 4-layer, но readback показывает inner layers как Signal вместо GND/PWR; SS14 diode-OR работает как reverse-blocking fallback, но лучше заменить на ideal-diode/power-mux перед производством. Critical ERC по питанию/GND для W5500, USB ESD, LMR16020 и PoE/DC OR-ing исправлены, placement выполнен на 80×100 мм.
Fix stackup and routing
Fix stackup
Allow larger board
Finish routing
Replace diode OR
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Rev A Readiness Review - Access Reader
Scope
This review checks the uploaded technical design before schematic capture. It combines the extracted PDF requirements with an independent architecture review. Status: not ready for blind schematic implementation; ready for structured Rev A planning.
Executive Summary
The architecture is feasible, but Rev A success depends on closing several design gates before wiring: ESP32-S3 GPIO allocation, power budget, RF floorplan and antenna tuning, PoE isolation, external-port protection, relay contact specification, DNP matrix and flash partition/wear plan.
Critical Findings
Table
| Priority | Area | Risk | Required action before schematic freeze |
|---|---|---|---|
| P0 | ESP32-S3 GPIO | Boot failures if GPIO0, GPIO3, GPIO45, GPIO46 or USB pins are loaded incorrectly | Create final GPIO allocation table with boot/default states |
| P0 | Power | 5 V and 3.3 V rails may be undersized if QR, RF, Ethernet, LEDs and both relays peak together | Complete worst-case budget and thermal check at 50 C enclosure |
| P0 | PoE | Isolation, creepage, RJ45 surge and flyback safety are not yet specified | Define PoE class, transformer, isolation boundary and layout constraints |
| P0 | RF antennas | NFC/LF/Wi-Fi/PoE coexistence can reduce read range or fail EMC | Define RF floorplan, copper keepouts, tuning networks and test pads |
| P1 | External interfaces | RS-485, Wiegand, inputs, USB, relay contacts and DC/RJ45 inputs need robust ESD/EFT/surge protection | Create per-port protection matrix and choose protection parts |
| P1 | SKU strategy | One PCB with DNP groups can cause backfeed or assembly mistakes | Create formal SKU-A/SKU-B DNP matrix and no-backfeed scheme |
| P1 | Relay outputs | Contact rating and suppression for inductive loads are underdefined | Freeze NO/NC/COM, AC/DC rating, inductive-load warning and snubber footprints |
| P1 | Memory/security | 50k credentials plus 20k events, OTA and flash encryption need partition/wear analysis | Create ESP-IDF partition plan and verify no external memory needed |
ESP32-S3 GPIO Gate
Required constraints:
- GPIO0 only for BOOT/test access with correct pull-up.
- GPIO19/GPIO20 reserved for native USB D-/D+.
- Avoid GPIO45 and GPIO46 for external active controls; GPIO45 needs a defined pulldown boot state.
- Avoid using boot-sensitive pins for relay drive, RS-485 DE, Wiegand, LEDs or externally-driven inputs.
- Relay and Wiegand outputs must default to safe inactive state during reset and boot.
- Shared SPI bus is allowed only if CLRC663 and W5500 have separate CS, RST and IRQ, and MISO tri-state behavior is verified.
Power Gate
Current conclusion from preliminary budget:
- Keep 3.3 V buck at 2 A class.
- Treat 5 V as at least 1.3 to 1.5 A peak rail in Rev A, with extra margin if GM861 actual illumination current is higher than the PDF estimate.
- 802.3af is likely feasible if the real worst-case stays below about 6.5 W, but class 3 should be assumed until measured.
- Add power-good/reset strategy and brownout behavior.
RF and Layout Gate
Required Rev A floorplan rules:
- ESP32 module antenna at board edge with all-layer keepout per Espressif datasheet.
- NFC 13.56 MHz coil and LF 125 kHz coil must have reserved mechanical area, copper restrictions and tuning networks.
- Do not place switching inductors, PoE transformer, RJ45 magnetics or relays inside RF antenna zones.
- Add RF/LF test pads and tuning DNP arrays.
- Firmware must time-multiplex NFC and LF excitation.
PoE and Safety Gate
Required decisions:
- IEEE 802.3af class target and maximum PD power.
- Isolated flyback transformer and feedback strategy.
- Creepage/clearance and isolation slot rules.
- RJ45 shield/chassis strategy for a plastic enclosure.
- Ethernet TVS, common-mode behavior and surge path.
- No copper crossing the primary/secondary isolation boundary.
External Protection Matrix
Table
| Port | Required protection or design feature |
|---|---|
| DC input | Fuse/PTC, reverse-polarity MOSFET, TVS, LC or pi EMI filter |
| PoE RJ45 | Ethernet TVS, magnetics, shield strategy, PoE front-end protection |
| RS-485 | TVS on A/B, optional CMC, selectable termination and bias, failsafe transceiver |
| Wiegand | External-voltage-tolerant open-drain drivers, TVS, series resistors |
| Relay contacts | Snubber/TVS/MOV footprints, clearance and install-manual suppression guidance |
| Opto inputs | Current limit, reverse protection, TVS/RC filter, defined voltage thresholds |
| USB service | USB ESD array, shield/ground strategy, production lock-down policy |
| Tamper/buttons | ESD and debounce/filtering |
SKU Matrix Required Before Schematic Freeze
Table
| Block | SKU-A DC + Wi-Fi | SKU-B PoE + Ethernet |
|---|---|---|
| 9-32 V DC input and TPS54360B | Populate | DNP unless dual-input option is intentionally supported |
| PoE PD, flyback, RJ45 magnetics | DNP | Populate |
| W5500 Ethernet | DNP or optional | Populate |
| ESP32 Wi-Fi/BLE | Populate and active | Populate; Wi-Fi fallback or disabled by firmware |
| 5 V common rail | From DC buck | From PoE flyback secondary |
| No-backfeed components | Required | Required |
| SKU detect strap | Required | Required |
Open Questions to Close
- Exact GM861 connector, pinout, supply voltage and peak illumination current.
- Relay contact configuration and whether inductive loads are officially supported.
- Input voltage thresholds for opto inputs: dry contact only, 5 V, 12 V, 24 V or wider.
- RS-485 isolation requirement and maximum cable length.
- Wiegand external pull-up voltage range.
- PoE class and whether 802.3at should remain a fallback.
- Required card read distance after enclosure and metal-mounting effects.
- Whether external flash/FRAM is needed for log/database wear.
Recommended Next Step
Do not start full schematic wiring until the main-component list, GPIO allocation, power budget and SKU matrix are locked. The next productive step is to create a Rev A implementation plan and then add only the main components block-by-block with datasheet-backed support circuits.
Scope
Executive Summary
Critical Findings
ESP32-S3 GPIO Gate
Power Gate
RF and Layout Gate
PoE and Safety Gate
External Protection Matrix
SKU Matrix Required Before Schematic Freeze
Open Questions to Close
Recommended Next Step
