Access Reader Design
Access Reader — важная правка по РАЗМЕЩЕНИЮ разъёмов (ты на placement): ВСЕ разъёмы и клеммники ставь ПО КРАЮ платы, ориентированными наружу, с зазором под вставку кабеля/штекера. Сейчас RJ45 Ethernet стоит ПОСЕРЕДИНЕ — в него физически не воткнуть провод, перемести на кромку. На край разъёмной стороной наружу: RJ45 (Ethernet), клеммник входа 9–32В DC, клеммники 2 реле (NO/NC/COM), сервисный USB, клеммники/хедеры RS-485, Wiegand и 2 входов, разъём/шлейф GM861 (QR), 2-pin разъём катушки 125к (J101). Вход кабеля не должен перекрываться компонентами, крепёжными отверстиями или соседними разъёмами (проверь высоту/вылет коннектора наружу за контур). Зону поднесения карт (антенны 13.56/125к) держи свободным краем без разъёмов. Это правило — жёсткое: неудобный доступ к разъёму = брак. Обнови placement и manufacturing notes, отметь этот constraint в ready-to-export чеклисте.
Worked for 4 mins 30 sec
Created a project doc
Access Reader Factory Package Run — 2026-07-09
Full first Rev A prototype preserved: PoE AG9905-MTB, RJ45/W5500 Ethernet, 9-32 V DC LMR16020 branch and ESP32-S3 Wi-Fi are populated. Criti...
Сделал автономный проход и экспортировал артефакты; все ссылки на Gerber+drill, BOM, BOM с DNP-колонкой и Pick-and-Place собраны в Access Reader Factory Package Run — 2026-07-09.
Что не удалось: пакет не order-ready — routing не завершён, DRC всё ещё показывает много airwires; stackup tool принял 4-layer, но readback показывает inner layers как Signal вместо GND/PWR; SS14 diode-OR работает как reverse-blocking fallback, но лучше заменить на ideal-diode/power-mux перед производством. Critical ERC по питанию/GND для W5500, USB ESD, LMR16020 и PoE/DC OR-ing исправлены, placement выполнен на 80×100 мм.
Fix stackup and routing
Fix stackup
Allow larger board
Finish routing
Replace diode OR
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Rev A Implementation Plan - Access Reader
Purpose
This plan converts the uploaded technical design and pre-review findings into the next engineering actions for schematic Rev A.
Decision
Proceed with a full first Rev A prototype on one PCB: populate both PoE/Ethernet and 9-32 V DC/Wi-Fi paths. The first schematic pass must lock core components, GPIO allocation, safe 5 V OR-ing, power architecture and external protection before detailed RF tuning or final layout.
Stage 0 - Close Pre-Schematic Gates
Table
| Gate | Output | Status |
|---|---|---|
| GPIO allocation | ESP32-S3 pin table with boot states and reset defaults | Open |
| Power budget | Datasheet-backed rail currents and PoE class | Draft estimate exists |
| Population matrix | Full prototype population and no-backfeed scheme | Updated: PoE/W5500/RJ45 and DC buck all populated |
| RF floorplan | Wi-Fi/NFC/LF/QR physical zones and keepouts | Open |
| Protection matrix | Per-port ESD/EFT/surge circuits | Draft exists |
| Memory plan | ESP-IDF partition and wear plan | Open |
Stage 1 - Add Main Schematic Blocks
Add only main components first, then wire support circuits after datasheet checks.
-
Core MCU and service interface
- ESP32-S3-WROOM-1-N16R2
- BOOT/RESET, native USB service, test pads
- Secure production/debug assumptions
-
Power entry and rails
- 9 to 32 V protected DC input and LMR16020 5 V buck
- AG9905-MTB 802.3af PoE module path
- Reverse-blocking ideal-diode OR / priority power mux into
5V_SYS - Common 5 V and 3.3 V regulators, power-good/reset
-
Communications
- W5500 Ethernet populated in first prototype
- RS-485 transceiver
- Wiegand output drivers
-
Credential readers
- GM861 QR connector and power switch
- CLRC663 plus NFC front-end with matching placeholders
- EM4095 LF front-end with coil connector/tuning placeholders
-
Access I/O and UI
- Two relay drivers and Form C terminal blocks
- Two isolated inputs and tamper
- WS2812B/status indication and buzzer
- RTC PCF8563 and backup battery
Stage 2 - Datasheet-Backed Support Circuits
For each IC, verify and add:
- Required decoupling and bulk capacitors.
- Pull-ups/pull-downs, boot straps and reset networks.
- Recommended regulator compensation/inductor/capacitor values.
- Interface protection and termination.
- RF matching/tuning placeholders and test pads.
Stage 3 - Schematic Verification
- Run ERC/design review.
- Check all power pins, grounds, no-connects and support passives.
- Check external-port voltage tolerance and protection.
- Verify relay default-off state and Wiegand default-high/open state.
- Verify ESP32 boot and USB download path.
Stage 4 - Layout Checkpoint
Pause before PCB layout routing. Required before layout starts:
- Board/enclosure size or at least antenna/mechanical zones.
- ESP32 antenna edge placement and keepout.
- NFC/LF antenna dimensions and test strategy.
- PoE isolation boundary and creepage rules.
- Connector side/orientation and mounting plan.
Recommended Immediate Next Action
Start with component sourcing and datasheet verification for the core blocks: ESP32-S3-WROOM-1-N16R2, GM861 connector/module data, CLRC663 plus, EM4095, W5500, TPS54360B, PoE PD/flyback option, 3.3 V buck, relays and external protection devices. Then add the main components to the schematic block by block.
Purpose
Decision
Stage 0 - Close Pre-Schematic Gates
Stage 1 - Add Main Schematic Blocks
Stage 2 - Datasheet-Backed Support Circuits
Stage 3 - Schematic Verification
Stage 4 - Layout Checkpoint
Recommended Immediate Next Action
