• Indoor wall or turnstile-mounted access reader, initial target: 0 to 50 C, up to 95 percent RH non-condensing.
• Prototype path: MVP on modules, then custom single-PCB Rev A EVT, Rev B DVT/pilot, then certification/series.
• Device must keep granting/denying access when network connectivity is lost.

• Read QR and 1D/2D barcodes from paper and phone screens.
• Read Mifare Classic/Plus/DESFire, ISO14443/ISO15693/NFC tags, and Android/iOS NFC flows where supported.
• Read 125 kHz EM-Marine class cards/tags.
• Store at least 50000 credentials and 20000 events locally.
• Synchronize with a1Aplatform over MQTT/TLS, with WebSocket fallback.
• Drive two relay outputs as dry contacts.
• Expose Wiegand output and RS-485/OSDP-style integration.
• Provide RGB indication, buzzer, tamper detection, service USB, RTC backup.

• ESP32-S3-WROOM-1-N16R2 module with Wi-Fi/BLE, secure boot and flash encryption.
• QR scanner module: GROW GM861 family, UART interface.
• 13.56 MHz NFC front-end: NXP CLRC663 plus, SPI interface, tuned PCB antenna.
• 125 kHz LF front-end: EM4095 with tuned coil antenna.
• First Rev A prototype: one fully populated board with 9 to 32 V DC input, IEEE 802.3af PoE using AG9905-MTB, W5500 Ethernet/RJ45 and ESP32-S3 Wi-Fi all populated.
• Two relays, Form C target: NO/NC/COM, at least 2 A at 30 VDC.

Diagram

• ESP32-S3-WROOM-1-N16R2 preferred because 16 MB flash and 2 MB PSRAM support local database, TLS, OTA and buffering.
• Secure boot v2, flash encryption, signed OTA and unique device credentials are required.
• GPIO map must avoid ESP32-S3 boot-strapping conflicts and reserve GPIO19/GPIO20 for native USB.

• Common internal architecture: selected input source creates 5 V, then a 5 V to 3.3 V buck powers logic/RF.
• Protected 9 to 32 V DC input feeds an LMR16020 buck to 5V_DC_PRE_OR.
• RJ45 PoE path feeds AG9905-MTB 802.3af module output 5V_POE_PRE_OR.
• 5V_DC_PRE_OR and 5V_POE_PRE_OR must not be directly paralleled; they merge only through reverse-blocking ideal-diode OR-ing or a priority power mux into 5V_SYS.
• Power architecture must prevent backfeed between DC and PoE inputs when either or both sources are connected.

• QR: UART scanner module with MOSFET power switch and trigger/control lines.
• NFC: CLRC663 plus with matching/tuning network and RF test points.
• LF: EM4095 with coil tuning network and software time-multiplexing against NFC.

• Two relay outputs, dry contacts only. The device must not power locks or actuators.
• RS-485 with TVS, optional termination/bias and preferably isolation for long cable runs.
• Wiegand output through voltage-tolerant open-drain drivers, not direct ESP32 GPIO.
• Two isolated inputs for door/REX signals plus tamper input.

• No battery runtime target; RTC backup uses CR1220-class cell.
• PoE power target from PDF: less than 6.5 W, intended to fit IEEE 802.3af class 0 to 3.
• Firmware should limit WS2812 brightness and time-multiplex RF channels to reduce peak draw and interference.

• Single 4-layer PCB, signal/GND/power/signal stackup target.
• First prototype BOM populates both DC and PoE/Ethernet branches on one PCB; PoE, W5500 and RJ45 are not DNP for this build.
• Test pads are required for power rails, ESP32 boot/reset/USB/UART, SPI, I2C, RS-485, relay drives, NFC/LF tuning and QR UART.
• RF tuning variants must be supported by DNP capacitors/resistors.
• Board outline target is 80 × 100 mm. Size may increase only if required by antenna, keepout or mounting clearance; absolute maximum is 120 × 100 mm.
• Four M3 / Ø3.2 mm board mounting holes are required near the corners, with about 5 mm center inset from edges and at least 6 mm copper/component keepout around each.
• The 13.56 MHz NFC antenna is required in Rev A as an on-board printed loop, not deferred to EVT; matching/EMC parts remain tuning placeholders for EVT.
• The 125 kHz LF antenna is required in Rev A as a 2-pin external coil connector plus tuning placeholders; the external coil is tuned at EVT.

• ESP-IDF target recommended.
• Partition plan must reserve two OTA slots, NVS, certificates, database, event log, crash dumps and wear-leveling storage.
• Firmware should detect active transport/power state where available; Ethernet and Wi-Fi are both present in the first prototype.
• Production provisioning must load keys/certificates, enable secure boot/flash encryption and define service USB/debug lock-down.

• Narrow vertical enclosure with top QR window and lower card/phone presentation area.
• ESP32 antenna at PCB edge with all-layer antenna keepout.
• NFC and LF antenna area must avoid copper planes/components as required by tuning design.
• PoE flyback, DC/DC inductors, RJ45 magnetics and relays must be kept away from RF antenna zones.
• Indoor v1 target only; outdoor/IP65 version is a separate design pass.
• Card presentation edge should contain the 13.56 MHz printed loop and 125 kHz external coil connector/reserved zone, colocated enough for user interaction but kept away from noisy power/Ethernet/relay blocks.

• Use module-based ESP32-S3 instead of bare RF chip to reduce radio integration risk.
• Use local access decision path rather than cloud-only validation.
• Use W5500 for Ethernet because ESP32-S3 has no RMII Ethernet MAC.
• Use dry-contact relay outputs only; external lock power is out of scope.
• Treat NFC/LF antenna tuning as EVT validation work, not a guaranteed first-pass schematic constant.

• GM861 UART-level pinout, current and mechanical details will be verified from datasheet before schematic capture.
• Relay contact rating is 2 A at 30 VDC resistive unless updated.
• Inputs will support at least dry contact and 5 to 24 V field signaling, but thresholds are not yet frozen.
• PoE SKU targets 802.3af class 3 unless the final worst-case budget exceeds margin.
• No external memory is used in Rev A unless partition/wear analysis proves internal flash insufficient.

• Initial specification created from uploaded PDF and architecture review.
• Critical Rev A gates added: GPIO map, power budget, RF floorplan, PoE safety, protection matrix, SKU DNP matrix and memory/partition plan.
• 2026-07-09 antenna/mounting update: added requirements for H1–H4 M3 holes, U8 13.56 MHz printed loop antenna, CLRC663 matching/EMC placeholders, J101 external 125 kHz coil connector, LF tuning placeholders, all-layer NFC copper keepout and 120 × 100 mm board-size ceiling.