PDLC Controller
how do I send what we have to a PCB company to complete what i've already done so they can quote?
Thought for 33 sec
Best path: share the Flux project directly with the PCB designer/engineering firm, plus send them the project docs/specs; don’t send it as a fabrication package yet because the board still has unresolved airwires and is not manufacturing-ready. Flux docs say: “When working with other Flux users, you can simply share your project within Flux—there's typically no need to export files for collaboration purposes.” Source
For a quote to finish the design, send:
- Flux project link/access
- Project Specification, Architecture Overview, Validation Plan, Risk Register
- Note: “110 VAC mains-input PDLC controller, 25 W+, ~70 VAC square-wave output, ramp-up/ramp-down, safety-minded consumer design”
- Current status: schematic partly converted, PCB placed, routing incomplete
For manufacturing quote later, export Gerbers/BOM/pick-and-place only after DRC is clean; export guidance says airwires, overlapping copper, or missing footprints should block manufacturing export because the board may be unmanufacturable .
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Architecture Overview
One-Sentence Summary
This is a mains-input PDLC controller that converts 110 VAC into a supervised high-voltage drive system producing a controlled AC square-wave output for approximately 25 W nominal PDLC film loads, with ramp-up / ramp-down, sensing, and fault protection.
Top-Level Architecture
Diagram
Proposed Schematic Partitions
1. Mains Entry and Protection
Purpose
- Accept line, neutral, and protective earth safely.
- Survive common surge and user-installation events.
Major functions
- Fuse
- Surge clamp / MOV
- Inrush limiting strategy
- Protective earth handling
- Terminal labeling for line, neutral, and earth
Key design notes
- This block is entirely hazardous-voltage.
- Field wiring and fault containment begin here.
2. EMI Filter and Line Sense
Purpose
- Reduce conducted emissions and susceptibility.
- Provide line-presence and zero-cross reference information to the control system.
Major functions
- Common-mode / differential filtering
- Optional line-frequency / zero-cross sensing
- Line-state conditioning for control logic
Key design notes
- The uploaded ramp material indicates that startup behavior should be coordinated to line zero crossing or an equivalent controlled transient-reduction method.
3. Rectifier and Bulk HV DC Bus
Purpose
- Convert filtered AC mains into the internal high-voltage energy source used by the output power stage.
Major functions
- Bridge rectification
- Bulk storage capacitor bank
- Bus discharge / bleeder function
- Bus measurement divider
Key design notes
- This bus is the main energy reservoir for the 25 W-class output stage.
- Bus measurement should be available to the control block for fault management and startup sequencing.
4. Auxiliary Control Supply
Purpose
- Generate the low-voltage rails required by logic, sensing, and interface circuits.
Major functions
- Offline auxiliary conversion or equivalent housekeeping supply
- Post-regulation to digital/analog control rails
- Power-good / brownout qualification
- Local decoupling and sequencing
Key design notes
- Isolated vs non-isolated implementation is still a design choice to be frozen.
- Control rails must become valid before inverter enable.
5. Controller and Ramp Engine
Purpose
- Implement the product behavior visible to the user and installation interfaces.
Major functions
- ON/OFF behavior
- Ramp-up and ramp-down profile generation
- Frequency-mode selection: LINE, LINE/2, 32 Hz
- Fault latching / retry policy
- Mute / opaque override behavior
- Interface decoding for dry contact, 0-10 V, and RS-485 / DMX / COM style control
Key design notes
- This block is responsible for translating commands into output-state changes while avoiding abrupt film stress.
- The ramp deck indicates a gradual increase to nominal amplitude is preferred over abrupt application of full output.
6. Inverter Controller and Gate Drive
Purpose
- Translate the commanded operating mode into the switching signals that control the output power stage.
Major functions
- Frequency generation or synchronization
- Dead-time and shutdown control
- Gate-drive conditioning
- Primary-side current-limit hooks
Key design notes
- This block forms the boundary between logic decisions and power conversion.
- Protection must be able to disable this stage quickly on faults.
7. Power Inverter Stage
Purpose
- Convert energy from the HV bus into the PDLC drive waveform.
Major functions
- Switching bridge or push-pull stage
- Power semiconductors and thermal path
- Snubbers / clamps / damping
- Current sensing and fault feedback
Key design notes
- The inverter must be sized above the nominal 25 W load to preserve margin.
- The exact topology can still be selected during detailed design, but it must support square-wave PDLC output and controlled amplitude behavior.
8. Output Network and PDLC Interface
Purpose
- Present the correct AC waveform to the film and protect against dangerous DC or short-circuit conditions.
Major functions
- Output coupling / transformer or equivalent interface
- DC blocking function
- Output connector to PDLC film
- Output-voltage and output-current sensing
Key design notes
- The uploaded Gauzy manual explicitly calls out over-voltage, short-circuit, and DC-blocking protection.
- The film output remains a hazardous section and must be partitioned accordingly.
9. Status and External Interfaces
Purpose
- Provide external command and observability points.
Major functions
- Dry contact input(s)
- 0-10 V input
- RS-485 / DMX / COM option
- ALARM output
- OUT OK output
- Service/debug header
Key design notes
- External interfaces must be reviewed carefully if the auxiliary/control domain is non-isolated.
- Field wiring must be partitioned so installers cannot confuse control wiring with film or mains terminals.
Key System Signals
ACL,ACN,PEHVDC+,HVDC-AUX_VDD,3V3,5V_CTRLINV_EN,RAMP_CMD,MUTE_CMDMODE_LINE,MODE_LINE_DIV2,MODE_32HZOUT_VSENSE,OUT_ISENSE,BUS_SENSEALARM,OUT_OK
Protection Strategy
- Input-side: fuse, surge suppression, EMI filtering, inrush management
- Bus-side: bulk-bus supervision and controlled discharge
- Output-side: over-voltage response, short-circuit response, DC blocking
- Control-side: brownout-safe sequencing and immediate inverter shutdown on major faults
Open Architecture Decisions
- Isolated vs non-isolated control/communications domain
- Exact inverter topology and output coupling implementation
- Final output-voltage tolerance around the nominal 70 VAC target
- Exact ramp timing and whether amplitude is shaped purely in firmware, purely in analog hardware, or both
One-Sentence Summary
Top-Level Architecture
Proposed Schematic Partitions
1. Mains Entry and Protection
2. EMI Filter and Line Sense
3. Rectifier and Bulk HV DC Bus
4. Auxiliary Control Supply
5. Controller and Ramp Engine
6. Inverter Controller and Gate Drive
7. Power Inverter Stage
8. Output Network and PDLC Interface
9. Status and External Interfaces
Key System Signals
Protection Strategy
Open Architecture Decisions
