PDLC Controller

Thought for 26 sec

I can’t manually draw the PCB trace from Q1 D to T1 PRI_1 from chat. The tools available here can place/re-place components and check DRC, but individual trace routing is a separate editor/manual routing workflow; the placement guidance explicitly covers component movement and post-placement DRC, not per-trace routing .

Use this exact manual route in the PCB editor:

Net: PRI_A
From: Q1 D
To: T1 PRI_1
Route rule: top layer, shortest direct path, zero extra vias
Keep away from: control/timing nets around U2/U3
After routing: run DRC and confirm Q1/T1 airwires dropped with no copper overlap or clearance errors.

rgallizzi

how do I send what we have to a PCB company to complete what i've already done so they can quote?

Thought for 33 sec

flux

Best path: share the Flux project directly with the PCB designer/engineering firm, plus send them the project docs/specs; don’t send it as a fabrication package yet because the board still has unresolved airwires and is not manufacturing-ready. Flux docs say: “When working with other Flux users, you can simply share your project within Flux—there's typically no need to export files for collaboration purposes.” Source

For a quote to finish the design, send:

Flux project link/access
Project Specification, Architecture Overview, Validation Plan, Risk Register
Note: “110 VAC mains-input PDLC controller, 25 W+, ~70 VAC square-wave output, ramp-up/ramp-down, safety-minded consumer design”
Current status: schematic partly converted, PCB placed, routing incomplete

For manufacturing quote later, export Gerbers/BOM/pick-and-place only after DRC is clean; export guidance says airwires, overlapping copper, or missing footprints should block manufacturing export because the board may be unmanufacturable .

Generate quote package

Export manufacturing files

Create BOM spreadsheet

Generate STEP model

Files

Schematic

Layout

3D View

Validation Plan

Objectives

Verify the redesigned controller meets the 110 VAC mains-input requirement.
Verify safe operation at approximately 25 W PDLC load.
Verify AC square-wave output, frequency modes, and controlled ramp-up/ramp-down behavior.
Verify protection response, status reporting, and safe fault handling.

Validation Scope

This plan covers bench and design-review validation for the redesign baseline before PCB release. It focuses on the mains front end, auxiliary control supply, inverter/output stage, ramp behavior, and protection behavior associated with a single-channel PDLC controller inspired by the Gauzy FLEX DUO feature set.

Test Setup Assumptions

Use an isolated bench environment and qualified mains-safe measurement practices.
Use a representative PDLC-equivalent capacitive load fixture sized to the intended approximately 25 W nominal operating point.
Where practical, use a programmable AC source to exercise line and frequency conditions.
Use isolated or high-voltage differential probes for mains, HV bus, and output waveform measurements.

Test Matrix

Table

Test ID	Test	Method	Pass Criteria
V1	Input operating range	Apply 110 VAC nominal mains input	Controller starts and remains operational without abnormal heating or fault
V2	Housekeeping supply startup	Measure low-voltage rail at power-up	Control supply reaches valid rail before inverter enable
V3	Output steady-state voltage	Measure AC output with representative PDLC-equivalent load	Output reaches target nominal square-wave voltage in selected mode
V4	Frequency mode selection	Test line, line/2, and 32 Hz modes	Measured frequency matches selected mode
V5	Ramp-up behavior	Capture output waveform during enable	Output amplitude increases gradually from low level/zero-cross-aware startup to nominal value without destructive transient
V6	Ramp-down behavior	Capture waveform during disable/dim-down	Output amplitude reduces in controlled fashion without abrupt fault or overshoot
V7	Short-circuit protection	Temporarily short output under controlled conditions	Controller enters safe fault response and protects power stage
V8	Over-voltage / bus fault response	Induce defined abnormal input or internal fault condition	Output disables safely and fault/status output asserts correctly
V9	Thermal test	Run at nominal 25 W PDLC-equivalent load	Component temperatures remain within selected component limits
V10	Status interface	Observe ALARM / OUT OK behavior	Status outputs reflect healthy and faulted states correctly
V11	Zero-cross-related startup behavior	Capture line sense and output during startup	Startup occurs at or near the intended controlled phase / zero-cross strategy without destructive transient
V12	0-10 V control response	Sweep external control voltage from 0 V to 10 V	Output transparency command response is monotonic and bounded with no latch-up
V13	Dry-contact interface behavior	Exercise ON/OFF and dimming contact inputs	Controller follows commanded state changes without unsafe transitions
V14	RS-485 / DMX / COM command behavior	Inject valid protocol commands	Output state, mode, and status response match commanded values
V15	Mute / opaque override	Assert and release mute condition	Output transitions immediately to opaque-safe behavior and returns correctly when released

Instrumentation

Isolated differential oscilloscope probes for mains and PDLC output measurements
Power analyzer or wattmeter for input/output power
Thermal camera or thermocouples for hot-spot validation
Programmable AC source if line/frequency variation testing is required
Representative capacitive PDLC-equivalent load fixture

Measurements to Record

Input RMS voltage and frequency
Bulk HV bus voltage at startup, steady state, and shutdown
Auxiliary rail startup timing and minimum/maximum voltage
Output RMS voltage and waveform shape for each mode
Output operating frequency in LINE, LINE/2, and 32 Hz modes
Ramp-up and ramp-down duration and waveform envelope
Short-circuit trip behavior and recovery method
Thermal rise of the hottest power, magnetic, and control-supply components

Pass / Fail Notes

No uncontrolled output application at startup
No persistent DC at the film output under normal operation
No component exceeds its selected electrical or thermal limit during nominal-load testing
No unsafe fault persistence after output short or abnormal bus condition
ALARM / OUT OK signaling remains coherent with the actual controller state

Review Gates

Requirements review before detailed component selection
Architecture review before schematic completion
Safety and isolation review before layout
Bench validation review before pilot build

Validation Deliverables

Bench test log with oscilloscope captures of startup, shutdown, and fault events
Mode table with measured output voltage and frequency
Thermal summary with hotspot temperatures and ambient conditions
Open-issues list for any unmet behavior, derating concern, or protection anomaly

Objectives
Validation Scope
Test Setup Assumptions
Test Matrix
Instrumentation
Measurements to Record
Pass / Fail Notes
Review Gates
Validation Deliverables