Diagram

• Input supply: 12 V DC nominal external adapter
• PDLC output target: 42 V AC to 70 V AC square wave based on public Gauzy PDLC references
• Nominal operating frequencies to support: 25 Hz, 32 Hz, 50 Hz
• Separate low-voltage control and high-voltage output connectors for safety
• Include input protection, output isolation through transformer, and output voltage sensing
• Control rail: 3.3 V from local buck regulator

• PWM controller candidate: SG3525 / UC3525 family
• Logic supply buck regulator: TPS561208DDCR
• Control MCU candidate: STM32F030F4P6
• Inverter MOSFET candidate: IRLZ44N class device
• High-voltage output connector: 2-position 7.62 mm terminal block

• Public PDLC literature indicates low-power operation of roughly a few watts per square meter, but controller output current must be sized for the intended film area.
• Final transformer turns ratio and output current target depend on film load and reference photo clues.
• High-voltage and low-voltage domains should remain physically separated on the PCB.
• SG3525 support network was completed with SYNC bias, dead-time resistor, compensation RC, soft-start capacitor, and a first-pass feedback divider tied to a capacitively sampled secondary center node.
• TPS561208 support was tightened to follow the datasheet pattern more closely by explicitly wiring GND, VBST-to-SW bootstrap, enable from input power-good, and adding a 22 uF output capacitor.
• TPS26630 support was completed with ILIM, dVdT, PGTH, and MODE bias parts; because no external reverse-blocking FET is currently used, B_GATE and DRV are intentionally parked to ground and IN_SYS is tied to VIN.
• The current transformer choice in the schematic, SM91502ALE, is an isolation communications transformer with 1:1 ratio and is not a validated PDLC step-up transformer. The present HV stage should be treated as topological placeholder hardware until the required PDLC output voltage, frequency, load capacitance, and transformer ratio are confirmed.
• The present SG3525 timing values of RT = 100 kOhm and CT = 10 nF imply an oscillator frequency of about 1.42 kHz with RD = 100 Ohm, which does not match the earlier 25 Hz to 50 Hz PDLC target narrative. The timing network or architecture must be revised if true low-frequency direct drive is required.

• 110 VAC mains input consumer-oriented PDLC controller
• Approximately 25 W nominal PDLC load based on roughly 100 sq/ft at 0.25 W/sq ft
• AC square-wave output
• Controlled ramp-up and ramp-down behavior
• Architecture inspired by Gauzy FLEX DUO, but not a direct clone

• Gauzy FLEX DUO manual states Universal Input 110/240 VAC 50/60 Hz
• Output reference states 70 VAC square wave with selectable LINE, LINE/2, and 32 Hz operating modes, corresponding to 25/30/32/50/60 Hz depending on country and configuration
• Control methods described in the manual include high-voltage line trigger, dry contact, RS-485/DMX/COM, and 0-10 VDC control
• Protection functions described in the manual include over-voltage, short-circuit, and DC blocking
• Ramp-up reference notes that Gauzy controllers detect zero crossing on the input line and increase gradually the output signal to the LC film until reaching nominal amplitude to reduce transient stress on busbars

1. Mains entry and protection
   • 110 VAC line, neutral, and protective earth entry
   • fuse, MOV, EMI filter, and mains safety partition
2. Rectifier and bulk HV bus
   • bridge rectification and bulk energy storage for the output stage
3. Auxiliary control supply
   • low-voltage rail generation for controller, sensing, and status functions
4. Control and ramp engine
   • implements ON/OFF, ramp-up, ramp-down, mute, and frequency selection
5. Inverter and output stage
   • generates PDLC drive waveform from the HV bus
6. PDLC output, sensing, and fault/status interfaces
   • output voltage/current sensing, ALARM, OUT OK, and external interface handling

• J2: 3-position mains terminal for Line / Neutral / Earth entry
• F1: 5x20 mm line fuse holder in series with Line
• RV1: 275 VAC MOV across Line-Neutral
• L2 and C20: common-mode choke plus X-class suppression capacitor for EMI filtering
• BR1: full-wave bridge rectifier creating a rectified HV bus
• C21 and R30: 100 uF / 450 V bulk storage capacitor with bleeder discharge path
• PS1: isolated 5 V auxiliary AC-DC module for the low-voltage control domain

• Mains and user-accessible control sections must be explicitly partitioned
• The earlier 12 V DC input stage and related component choices are obsolete and have been removed from the schematic baseline
• AC mains layout should maintain clear high-voltage and low-voltage zoning with at least 6 mm clearance and creepage across the isolation boundary as a conservative PCB rule for mains separation
• The isolated auxiliary module is the intended schematic boundary between the hazardous mains/HV bus domain and the low-voltage control domain

• U4: MCP1700T-3302E/TT added as the dedicated 5 V to 3.3 V LDO for the control domain
• C22: 10 uF input capacitor from AUX_5V_CTRL to GND
• C23: 10 uF output capacitor from 3V3 to GND
• C24: 100 nF high-frequency bypass capacitor from 3V3 to GND
• PS1:+VO now feeds the new AUX_5V_CTRL net into U4:VI
• U4:VO now drives the project 3V3 net used by the control-domain circuitry

• PS1 provides isolated 5 V housekeeping power from the mains side
• U4 derives the final 3.3 V logic rail for:
  • U2 MCU core supply pins
  • local low-voltage decoupling and support parts already on the 3V3 net
• The low-voltage redesign intentionally replaces the earlier local buck-regulator assumption for the control domain with a simpler post-regulated LDO stage referenced to the isolated output of PS1

• Confirm any residual TPS561208 buck-regulator remnants are fully isolated or removed from the control-domain path
• Confirm all low-voltage pull-ups and support rails that should be on 3V3 are not still tied to stale supply assumptions
• Re-run targeted ERC and decoupling review after the remaining obsolete buck circuitry is cleaned up

• Removed L1, R5, and R7, which had remained only as vestigial buck-switch and feedback-path artifacts
• Removed R26, R27, R28, R29, and C19, which were residual input-protection/eFuse support parts no longer tied to an installed controller

• PS1:+VO now directly feeds AUX_5V_CTRL
• AUX_5V_CTRL now supplies both U4:VI and U3:VC
• U4:VO remains the sole source of the active 3V3 control rail
• The old stale net labels BUCK_SW and BUCK_FB were eliminated from the live power path by removing their remaining attached components

• The intended control-domain supply path is now:
  • PS1 -> AUX_5V_CTRL -> U4 -> 3V3
• Targeted ERC checks passed after cleanup with no reported floating-pin, missing-power, single-pin-net, or undriven-net issues
• Remaining low-voltage capacitors such as C15 are now simply bulk capacitance on 3V3 even if their legacy role text still reflects the earlier buck-based implementation