Part Metadata Audit

flux

Applied the functional grouping and verified it.
What changed:
  • Corrected pin labels for pins 6, 7, and 8.
  • Renamed pads 50–53 to EP_ANCHOR1 through EP_ANCHOR4.
  • Assigned exactly one primary Pin Group per terminal: Power, Ground, Reference, Boot, Oscillator, Debug, Analog, PWM, or SPI.
  • Added Pin Type, Pin Description, and 3.3V voltage metadata for the power pins.
I used supported group labels for clean metadata, while keeping the detailed function in each pin description.
adrian95

adrian95

Please also place each terminal into its corresponding section.

flux

I’ll set each terminal’s Section property to match its primary functional group, keeping each pin in only one section, then verify the metadata.

flux

Done. I placed every terminal into a Section aligned to its primary function, with no duplicate section assignment per pin.
I normalized the section names to supported values:
  • Power rails and grounds → Power
  • Exposed pad / corner anchors → Other
  • Reset pin → Reset
  • Oscillator pins → Clock
  • Programming/JTAG pins → Debug
  • Analog/op-amp/ADC/DAC pins → Analog
  • PWM pins → Peripheral
  • SPI pins → Serial
Verified the terminal metadata after applying the changes.
Run ERC/DRC
Verify with datasheet
Clean pin descriptions
Review Other pins
RP56/ASDA1/SCK2/RC8
Pin Number
28
PGC1/AN11/RP41/SDA1/RB9
Pin Number
37
~MCLR
Pin Number
5
RP52/PWM5H/ASDA2/RC4
Pin Number
38
OA1IN-/ANA1/RA1
Pin Number
9
PGD3/RP37/PWM6L/SDA2/RB5
Pin Number
33
VSS_2
Pin Number
31
VSS_3
Pin Number
42
PGD1/AN10/RP40/SCL1/RB8
Pin Number
36
RP60/PWM8H/RC12
Pin Number
3
OA3OUT/AN4/CMP3B/IBIAS3/RA4
Pin Number
12
TDI/RP44/PWM2H/RB12
Pin Number
47
VDD_2
Pin Number
32
RP47/PWM1L/RB15
Pin Number
2
VDD_1
Pin Number
18
OA3IN+/AN14/CMP2B/ISRC1/RP50/RC2
Pin Number
16
RP72/SDO2/PCI19/RD8
Pin Number
30
ANN2/RP77/RD13
Pin Number
6
AN17/ANN1/IBIAS1/RP54/RC6
Pin Number
17
AN12/ANN0/RP48/RC0
Pin Number
7
RP46/PWM1H/RB14
Pin Number
1
RP53/PWM5L/ASCL2/RC5
Pin Number
39
RP59/PWM7L/RC11
Pin Number
41
VDD_3
Pin Number
43
TDO/AN2/CMP3A/RP39/SDA3/RB7
Pin Number
35
AVSS
Pin Number
14
DACOUT1/AN3/CMP1C/RA3
Pin Number
11
RP61/PWM8L/RC13
Pin Number
4
AN15/CMP2A/IBIAS2/RP51/RC3
Pin Number
20
OA3IN-/AN13/CMP1B/ISRC0/RP49/RC1
Pin Number
15
OA1IN+/AN9/RA2
Pin Number
10
PGC3/RP38/PWM6H/SCL2/RB6
Pin Number
34
RP57/ASCL1/SDI2/RC9
Pin Number
29
RP58/PWM7H/RC10
Pin Number
40
OSCI/CLKI/AN5/RP32/RB0
Pin Number
21
RP65/PWM4H/RD1
Pin Number
44
TCK/RP43/PWM3L/RB11
Pin Number
46
TMS/RP42/PWM3H/RB10
Pin Number
45
OA1OUT/AN0/CMP1A/IBIAS0/RA0
Pin Number
8
AVDD
Pin Number
13
RP45/PWM2L/RB13
Pin Number
48
VSS_1
Pin Number
19
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DSPIC33CK128MP205-I/M4

DSPIC33CK128MP205-I/M4 thumbnail
dsPIC dsPIC™ 33CK, Functional Safety (FuSa) Microcontroller IC 16-Bit 100MHz 128KB (128K x 8) FLASH 48-UQFN (6x6)
28/36/48/64/80-Pin Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data (CAN FD)
perating Conditions • 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS • 3.0V to 3.6V, -40°C to +150°C, DC to 70 MIPS Core: 16-Bit dsPIC33CK CPU • 32-256 Kbytes of Program Flash with ECC and 8-24K RAM • Fast 6-Cycle Divide • LiveUpdate • Code Efficient (C and Assembly) Architecture • 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle, Mixed-Sign MUL Plus Hardware Divide • 32-Bit Multiply Support • Four Sets of Interrupt Context Saving Registers which Include Accumulator and STATUS for Fast Interrupt Handling • Zero Overhead Looping • RAM Memory Built-In Self-Test (MBIST) Clock Management • Internal Oscillator • Programmable PLLs and Oscillator Clock Sources • Reference Clock Output • Fail-Safe Clock Monitor (FSCM) • Fast Wake-up and Start-up • Backup Internal Oscillator Power Management • Low-Power Management Modes (Sleep, Idle, Doze) • Integrated Power-on Reset and Brown-out Reset High-Speed PWM • Eight PWM Pairs • Up to 250 ps PWM Resolution • Dead Time for Rising and Falling Edges • Dead-Time Compensation • Clock Chopping for High-Frequency Operation • PWM Support for:
  • DC/DC, AC/DC, inverters, PFC, lighting
  • BLDC, PMSM, ACIM, SRM motors • Fault and Current Limit Inputs • Flexible Trigger Configuration for ADC Triggering Timers/Output Compare/Input Capture • One General Purpose Timer • Peripheral Trigger Generator (PTG):
  • Up to 15 trigger sources to other peripheral modules
  • CPU independent state machine-based instruction sequencer • Nine MCCP/SCCP modules which Include Timer, Capture/Compare and PWM:
  • One MCCP
  • Eight SCCPs
  • 16 or 32-bit time base
  • 16 or 32-bit capture
  • 4-deep capture buffer • Fully Asynchronous Operation, Available in Sleep Modes

Properties

Official Microchip dsPIC33CK256MP508 Family Data Sheet DS70005349 applies to dsPIC33CK128MP205-I/M4; /M4 is 48-lead UQFN 6x6 mm with exposed pad.

dsPIC33CK128MP205-I/M4

Microchip

Integrated Circuits

microchip.com/downloads/aemDocuments/documents/MCU16/ProductDocuments/DataSheets/dsPIC33CK256MP508-Family-Data-Sheet-DS70005349.pdf

IC

parametric-v1

creativecommons.org/licenses/by/4.0/

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