PCB Design for Fog Generator
Worked
Stopped by execution credits before I could finish the full schematic update or run ERC.
Completed so far:
- Removed obsolete 14 V parallel ideal-diode mux parts: U10/U11, Q10/Q11, C1/C2, R1–R4.
- Removed old TPS563200 17 V buck section: U3, L1, C5–C9, R5–R7.
- Removed old pump MOSFET driver and 2-pin pump connector: Q2, R16, R17, D2, J4.
- Renamed global power nets:
+14V_BUS→+28V_BUS+14V_MUX→+28V_OR_PRE_FUSEVBAT_A_IN→VBAT_SERIES_INPUMP_PWM→STEPPER_STEP
- Added main new 28 V architecture parts:
- U_BB LM5175PWPT buck-boost controller
- U3 TPS54561DPRT wide-VIN 3.3 V buck regulator
- J12 logical 6-pin LEMO input connector
- J4 5-pin JST-XH stepper pump connector
- U_DIODE_1/U_DIODE_2 LM74700-Q1 ideal-diode OR controllers
- Q_DIODE_1/Q_DIODE_2/Q_BB1–Q_BB4 using TSM170N06CP_ROG 60 V / 38 A MOSFETs as library substitutes because FDP18N40 was not found
- L_BB 47 µH / 15 A generic inductor placeholder
- Added and partially wired:
- LEMO input filter caps
- LM5175 bootstrap, soft-start, compensation, RT, UVLO, and feedback passives
- LM74700 1 µF VCAP bypass caps and gate networks
- TPS54561 input/output caps, bootstrap cap, feedback divider, EN/UVLO, SS, RT, and compensation placeholders
- Stepper connector pins for
+28V_BUS,GND,STEPPER_STEP,STEPPER_DIR,STEPPER_ENABLE
- Updated existing metadata:
- C3 to 4700 µF / 50 V bulk
- C4 to 50 V HF bypass
- F1 marked 25 A / 50 V minimum requirement
- J3 heater label/role updated for 28 V 200 W
- Q1 metadata updated to the 60 V MOSFET substitute
Important unresolved items:
- ERC has not been run after these edits.
- LM5175 datasheet correction: LM5175 VIN max is 42 V, not 60 V. It may still work for a 28 V system, but it is not a 60 V input controller.
- The exact LEMO EGG.1B.306 library footprint was not found; J12 is currently a logical 6-pin connector placeholder.
- The LM5175 current-sense implementation is only placeholder-wired; the proper high-power current-sense resistor/network still needs detailed design.
- INA226 monitor wiring is not fully resolved after the architecture change; U6B/R21 are still in an intermediate/orphaned state and need reconnection to the intended +28 V measurement point.
- PCB layout is now invalid for this revised architecture and will need a fresh placement/routing pass after the schematic is cleaned.
Clean unresolved issues
Run ERC/DRC
Find 60V controller
Find LEMO footprint
Design current sense
Refine this doc
Ask about this doc
Final Schematic Design Review — Phantom Fogger Control Unit V1
Review Timestamp
Automated checks were run on 2026-05-26 after the final UI/USB block was added.
Executive Summary
The schematic is complete enough to proceed to PCB layout. Schematic-level ERC and component-support checks are clean: no open ERC errors/warnings were reported for floating pins, power pins, pin-to-pin conflicts, single-pin nets, no-connect misuse, decoupling capacitors, capacitor voltage rating, parts availability, or missing footprints.
The PCB review is not clean yet because the board has not been placed/routed for the final 80 mm × 60 mm layout. Current DRC errors are physical-layout issues: airwires and overlapping copper from the provisional/auto placement. These are expected to be resolved during the next layout phase.
Power Tree Integrity
Rails
VBAT_A_INandVBAT_B_IN: independent V-mount inputs.VBAT_A_IDEAL_INandVBAT_B_IDEAL_IN: post-shunt/pre-ideal-diode input nodes.+14V_MUX: ideal-diode ORed battery output before the main fuse.+14V_BUS: fused high-current distribution rail, marked Max Current 25 A.+3V3: TPS563200 buck output, marked Max Current 3 A.GND: single common PCB ground reference.
IC Power and Decoupling
- U1 ESP32-S3-WROOM-1-N16:
3V3to+3V3; all GND pins tied toGND; local 10 µF + 0.1 µF decoupling present. - U3 TPS563200: VIN on
+14V_BUS; input 10 µF + 0.1 µF, output 22 µF + 0.1 µF, bootstrap 0.1 µF, EN pull-up, and feedback divider present. - U4 MAX31855: VCC to
+3V3, GND toGND; 10 µF + 0.1 µF local decoupling present. - U5 MAX3485: VCC to
+3V3, GND toGND; 0.1 µF local decoupling present. - U6A/U6B INA226: VS to
+3V3, GND toGND; local 10 µF + 0.1 µF decoupling present for each monitor. - U10/U11 LM74700-Q1: GND to
GND; VCAP bypass caps present; anode/cathode/gate networks present.
Result: Pass at schematic level.
Ground Integrity
GNDis the only common logic/power return net and is marked as a ground net.- DMX shield is isolated from PCB ground through the intended series network:
DMX_SHIELD→ R25 100 Ω →DMX_SHIELD_ISO→ C22 10 nF →GND. - No separate analog/digital/power ground nets were found in the functional schematic; thermocouple filtering returns to the common
GNDonly through the IC/reference network.
Result: Pass at schematic level.
MCU GPIO Assignment Review
No GPIO is assigned to two conflicting functions. Shared nets are intentional where applicable.
Table
| ESP32 Pin | Net | Function |
|---|---|---|
| IO0 | ESP32_BOOT_IO0 | BOOT button / bootloader entry |
| IO4 | HEATER_PWM | Heater MOSFET gate drive and heater-active LED indicator |
| IO5 | PUMP_PWM | Pump MOSFET gate drive |
| IO6 | FAN_PWM | Reserved fan PWM |
| IO7 | STATUS_LED_1 | UI header status LED 1 drive through R31 |
| IO8 | STATUS_LED_2 | UI header status LED 2 drive through R32 |
| IO9 | ENCODER_A | UI encoder A with pull-up |
| IO10 | ENCODER_B | UI encoder B with pull-up |
| IO11 | ENCODER_BTN | UI encoder button with pull-up |
| IO12 | SPI_MOSI | Reserved/shared SPI MOSI; not used by MAX31855 |
| IO13 | SPI_MISO | MAX31855 SO |
| IO14 | SPI_SCK | MAX31855 SCK |
| IO15 | SPI_CS_MAX31855 | MAX31855 chip select |
| IO16 | I2C_SDA | Shared I2C bus for INA226 and UI/OLED |
| IO17 | I2C_SCL | Shared I2C bus for INA226 and UI/OLED |
| IO18 | DMX_UART_RX | MAX3485 RO |
| IO19 | USB_D_N | Native USB D- to J1/J9 |
| IO20 | USB_D_P | Native USB D+ to J1/J9 |
| IO21 | DMX_UART_TX | MAX3485 DI |
| IO35 | DMX_DIR | MAX3485 DE and ~RE |
| IO36 | HEATER_CURRENT_SENSE | Reserved analog current sense |
| IO37 | FAULT_LED | Amber fault LED |
Notes:
- IO4 intentionally drives both Q1 gate network and the heater-active indicator through a 330 Ω LED resistor.
- IO19/IO20 go to both USB-C connector symbols J1 and J9; if both physical connectors remain populated, only one should be connected to a host at a time, or one connector should be removed/marked DNP before layout.
Result: Pass, with USB connector duplication to resolve as a product decision.
Current Path and Layout Requirements
Heater Path
- Nominal heater current: 200 W / 14.4 V ≈ 13.9 A.
- Nets marked for high current:
+14V_BUS,HEATER_POS_FUSED,HEATER_SW,HEATER_SHUNT_HI. - Q1 MOSFET selected for low RDS(on) and high current margin; shunt is 5 mΩ 2512 class.
Layout requirement:
- Use copper pours/polygons, not thin traces, for the heater path.
- Use top/bottom copper in parallel with via stitching where current changes layers.
- Target at least 15 A continuous capability with thermal margin.
- Keep high-current loop compact: +14V_BUS → F2/J3 heater positive → heater load → J3 return → Q1 → shunt → GND.
Pump Path
- Pump load ~3 W / 12 V ≈ 250 mA.
- AO3400A has large margin; flyback diode present.
- Route
+14V_BUSto J4 andPUMP_SW/Q2 return for at least 1 A capability.
Result: Pass at schematic level; must be enforced in layout rules and copper geometry.
Thermal Considerations
Q1 Heater MOSFET
- Dissipation estimate using 14 A and 3.5 mΩ RDS(on): P ≈ I²R ≈ 0.69 W at 25 °C; more at hot junction.
- Requires broad drain/source copper, thermal vias, and isolation from thermocouple/analog section.
U3 Buck Regulator
- 3 A-capable buck; logic load is expected well below 3 A but ESP32 transients and LEDs/OLED require stable decoupling.
- Requires short VIN/SW/inductor/output loop, local input/output caps, and copper around GND/VIN/SW per datasheet layout recommendations.
Result: Pass for schematic; layout must include thermal copper and separation.
DRC / ERC Status
ERC / Schematic Checks
The following checks currently show no open errors or warnings:
- ERC floating pins
- ERC single-pin nets
- ERC undriven nets
- ERC power pin issues
- ERC pin-to-pin conflicts
- ERC no-connect misuse
- Decoupling capacitor review
- Capacitor voltage rating review
- Parts availability
- Missing footprints
DRC / PCB Checks
Current DRC is not clean because layout/routing is not complete.
- Airwires: present, expected before routing.
- Overlapping copper: present in the provisional placement, expected to be resolved by proper placement before routing.
- Layout summary: current board is 160 mm × 100 mm, 4 copper layers, all parts on top, low density; component bounding box is not yet arranged for the requested ~80 mm × 60 mm target.
- Congestion noted near the current USB/LED cluster around J9/R30/R33/D3.
Layout Transition Recommendations
Before routing:
- Resize board to approximately 80 mm × 60 mm, 4-layer stackup.
- Add M3 mounting holes at corners.
- Place high-current heater section near load connector edge with Q1, J3/F2, shunt, and bulk cap grouped together.
- Place analog thermocouple section (U4/J6/R18/R19/C16) away from Q1 heater switching loop and buck SW node.
- Place U3 buck near +14V_BUS entry but away from thermocouple inputs.
- Keep ESP32 antenna/USB connectors on board edge with keepout respected.
- Route high-current copper pours first, then power/ground, then USB/DMX/SPI/I2C, then low-speed UI.
- Re-run DRC after placement, before routing, and again after routing.
Final Gate
Schematic is ready to proceed to layout. PCB is not yet manufacturable until placement, copper pours, routing, and DRC remediation are completed.
Review Timestamp
Executive Summary
Power Tree Integrity
Rails
IC Power and Decoupling
Ground Integrity
MCU GPIO Assignment Review
Current Path and Layout Requirements
Heater Path
Pump Path
Thermal Considerations
Q1 Heater MOSFET
U3 Buck Regulator
DRC / ERC Status
ERC / Schematic Checks
DRC / PCB Checks
Layout Transition Recommendations
Final Gate
