PCB Design for Fog Generator
Worked
Stopped by execution credits before I could finish the full schematic update or run ERC.
Completed so far:
- Removed obsolete 14 V parallel ideal-diode mux parts: U10/U11, Q10/Q11, C1/C2, R1–R4.
- Removed old TPS563200 17 V buck section: U3, L1, C5–C9, R5–R7.
- Removed old pump MOSFET driver and 2-pin pump connector: Q2, R16, R17, D2, J4.
- Renamed global power nets:
+14V_BUS→+28V_BUS+14V_MUX→+28V_OR_PRE_FUSEVBAT_A_IN→VBAT_SERIES_INPUMP_PWM→STEPPER_STEP
- Added main new 28 V architecture parts:
- U_BB LM5175PWPT buck-boost controller
- U3 TPS54561DPRT wide-VIN 3.3 V buck regulator
- J12 logical 6-pin LEMO input connector
- J4 5-pin JST-XH stepper pump connector
- U_DIODE_1/U_DIODE_2 LM74700-Q1 ideal-diode OR controllers
- Q_DIODE_1/Q_DIODE_2/Q_BB1–Q_BB4 using TSM170N06CP_ROG 60 V / 38 A MOSFETs as library substitutes because FDP18N40 was not found
- L_BB 47 µH / 15 A generic inductor placeholder
- Added and partially wired:
- LEMO input filter caps
- LM5175 bootstrap, soft-start, compensation, RT, UVLO, and feedback passives
- LM74700 1 µF VCAP bypass caps and gate networks
- TPS54561 input/output caps, bootstrap cap, feedback divider, EN/UVLO, SS, RT, and compensation placeholders
- Stepper connector pins for
+28V_BUS,GND,STEPPER_STEP,STEPPER_DIR,STEPPER_ENABLE
- Updated existing metadata:
- C3 to 4700 µF / 50 V bulk
- C4 to 50 V HF bypass
- F1 marked 25 A / 50 V minimum requirement
- J3 heater label/role updated for 28 V 200 W
- Q1 metadata updated to the 60 V MOSFET substitute
Important unresolved items:
- ERC has not been run after these edits.
- LM5175 datasheet correction: LM5175 VIN max is 42 V, not 60 V. It may still work for a 28 V system, but it is not a 60 V input controller.
- The exact LEMO EGG.1B.306 library footprint was not found; J12 is currently a logical 6-pin connector placeholder.
- The LM5175 current-sense implementation is only placeholder-wired; the proper high-power current-sense resistor/network still needs detailed design.
- INA226 monitor wiring is not fully resolved after the architecture change; U6B/R21 are still in an intermediate/orphaned state and need reconnection to the intended +28 V measurement point.
- PCB layout is now invalid for this revised architecture and will need a fresh placement/routing pass after the schematic is cleaned.
Clean unresolved issues
Run ERC/DRC
Find 60V controller
Find LEMO footprint
Design current sense
Refine this doc
Ask about this doc
Power Copper / Plane / Stitching Pass Report
Date: 2026-05-27
Project: Phantom Fogger Control Unit V1
Summary
The requested power-copper pass was evaluated after signal autorouting. The current available layout operations can set routing rules, inspect DRC/airwires, add generic copper/zone geometry, and run autorouting, but they do not provide a safe way in this session to bind custom copper pours/planes/via arrays to specific schematic nets with the required geometry and solder-mask openings. Because of that, I did not create un-netted copper shapes that could give a false impression of electrical connectivity.
Actions completed
- Restored the high-current net minimum-width rule to 4.0 mm for:
- +14V_BUS
- HEATER_SW
- HEATER_SHUNT_HI
- VBAT_A_IN
- VBAT_B_IN
- Confirmed prior autoroute results and re-ran DRC/airwire review after restoring the 4 mm high-current rule.
- Preserved the ESP32 antenna protected keepout marker and review status.
- Documented the remaining manual layout requirements below.
Current routing/DRC status
After restoring the 4.0 mm high-current rule, review reports many remaining airwires. This is expected because the existing autorouted narrow traces do not satisfy the 4 mm high-current requirement and the board still needs true copper pours / plane regions.
The previous signal-route state before restoring the 4 mm rule had only 4 remaining USB-related airwires:
- J9 D+ to SJ2 pin 1
- duplicate J9 D+ pad tie
- ESP32 IO19 to J9 D-
- duplicate J9 D- pad tie
After enforcing 4 mm high-current routing rules, additional high-current/power airwires are intentionally exposed and must be completed with net-tied copper pours.
Required manual / net-tied copper implementation
1. HIGH_CURRENT_POWER copper pours
The following nets must be implemented as net-tied copper pours on Layer 1 and Layer 4, not as ordinary narrow traces:
- +14V_BUS
- HEATER_SW
- HEATER_SHUNT_HI
- VBAT_A_IN
- VBAT_B_IN
Required effective width: 4 mm minimum along all high-current paths.
Required via arrays:
- At every layer transition: at least 6 vias, 0.3 mm drill / 0.5 mm pad.
- Q1 drain to heater connector path: use very wide copper from Q1 drain/tab area through F2/J3 heater path to support 14 A continuous with SJ2 P1
- SJ2 P2 -> ESP32 IO20
- J9 D- -> ESP32 IO19
- Duplicate J9 D+/D- pad tie connections
SJ2 must remain physically inline with D+ and must not be bypassed.
5. Q1 heater MOSFET thermal copper
Required:
- Q1 drain / tab copper on Layer 1: at least 200 mm^2 exposed copper.
- Mirrored copper on Layer 4.
- At least 24 thermal vias between Layer 1 and Layer 4 under/near the MOSFET tab.
- Keep this copper tied to HEATER_SW / drain node as intended.
6. R15 heater shunt copper
Required:
- Wide copper pours on each shunt pad extending at least 5 mm beyond the body.
- 6 thermal vias per pad.
- Solder mask opening over exposed copper extending about 2 mm beyond the shunt for convective heat loss.
Reported numeric fields
Because the net-tied pours/via arrays were not created in this pass, the requested numeric confirmations are not yet valid:
- HIGH_CURRENT_POWER routed as 4 mm+ pours: not yet complete
- Layer 3 split plane: not yet implemented
- Ground stitching via count: not yet implemented
- USB-C airwires routed: not yet complete
- Q1 drain copper area: not measurable / not implemented
- R15 shunt copper area per pad: not measurable / not implemented
- Final unrouted nets count: not zero while power pours and USB D+/D- remain incomplete
Recommended next step
Use manual PCB copper-pour editing or a net-aware copper-pour tool to create the specified power/ground pours and stitching via arrays, then re-run DRC. Do not proceed to fabrication until the high-current paths are implemented as actual net-tied copper pours and the USB D+/D- service jumper path is physically routed.
Summary
Actions completed
Current routing/DRC status
Required manual / net-tied copper implementation
1. HIGH_CURRENT_POWER copper pours
2. Layer 3 power plane split
3. Layer 2 ground plane
4. USB-C airwires
5. Q1 heater MOSFET thermal copper
6. R15 heater shunt copper
Reported numeric fields
Recommended next step
