PCB Design for Fog Generator
Worked
Stopped by execution credits before I could finish the full schematic update or run ERC.
Completed so far:
- Removed obsolete 14 V parallel ideal-diode mux parts: U10/U11, Q10/Q11, C1/C2, R1–R4.
- Removed old TPS563200 17 V buck section: U3, L1, C5–C9, R5–R7.
- Removed old pump MOSFET driver and 2-pin pump connector: Q2, R16, R17, D2, J4.
- Renamed global power nets:
+14V_BUS→+28V_BUS+14V_MUX→+28V_OR_PRE_FUSEVBAT_A_IN→VBAT_SERIES_INPUMP_PWM→STEPPER_STEP
- Added main new 28 V architecture parts:
- U_BB LM5175PWPT buck-boost controller
- U3 TPS54561DPRT wide-VIN 3.3 V buck regulator
- J12 logical 6-pin LEMO input connector
- J4 5-pin JST-XH stepper pump connector
- U_DIODE_1/U_DIODE_2 LM74700-Q1 ideal-diode OR controllers
- Q_DIODE_1/Q_DIODE_2/Q_BB1–Q_BB4 using TSM170N06CP_ROG 60 V / 38 A MOSFETs as library substitutes because FDP18N40 was not found
- L_BB 47 µH / 15 A generic inductor placeholder
- Added and partially wired:
- LEMO input filter caps
- LM5175 bootstrap, soft-start, compensation, RT, UVLO, and feedback passives
- LM74700 1 µF VCAP bypass caps and gate networks
- TPS54561 input/output caps, bootstrap cap, feedback divider, EN/UVLO, SS, RT, and compensation placeholders
- Stepper connector pins for
+28V_BUS,GND,STEPPER_STEP,STEPPER_DIR,STEPPER_ENABLE
- Updated existing metadata:
- C3 to 4700 µF / 50 V bulk
- C4 to 50 V HF bypass
- F1 marked 25 A / 50 V minimum requirement
- J3 heater label/role updated for 28 V 200 W
- Q1 metadata updated to the 60 V MOSFET substitute
Important unresolved items:
- ERC has not been run after these edits.
- LM5175 datasheet correction: LM5175 VIN max is 42 V, not 60 V. It may still work for a 28 V system, but it is not a 60 V input controller.
- The exact LEMO EGG.1B.306 library footprint was not found; J12 is currently a logical 6-pin connector placeholder.
- The LM5175 current-sense implementation is only placeholder-wired; the proper high-power current-sense resistor/network still needs detailed design.
- INA226 monitor wiring is not fully resolved after the architecture change; U6B/R21 are still in an intermediate/orphaned state and need reconnection to the intended +28 V measurement point.
- PCB layout is now invalid for this revised architecture and will need a fresh placement/routing pass after the schematic is cleaned.
Clean unresolved issues
Run ERC/DRC
Find 60V controller
Find LEMO footprint
Design current sense
Refine this doc
Ask about this doc
Final V1 Schematic Review — Phantom Fogger Control Unit
Updated: 2026-05-26
Scope
Final schematic-mode review before PCB layout for the ESP32-S3 based battery-powered fog generator controller.
User follow-up confirmations
U6B decoupling
Confirmed: U6B (INA226 battery B monitor) has both local VS decoupling capacitors:
- C19 = 10 µF MLCC from +3V3 / U6B VS to GND
- C20 = 0.1 µF MLCC from +3V3 / U6B VS to GND
This matches U6A's configuration:
- C17 = 10 µF MLCC from +3V3 / U6A VS to GND
- C18 = 0.1 µF MLCC from +3V3 / U6A VS to GND
No additional U6B capacitor was needed.
Ideal-diode mux MOSFET designators
The ideal-diode input MOSFETs are now:
- Q10 = FDP8030L, battery A ideal-diode pass MOSFET, driven by U10 LM74700-Q1
- Q11 = FDP8030L, battery B ideal-diode pass MOSFET, driven by U11 LM74700-Q1
The heater MOSFET is Q1 = FDP8030L.
USB-C duplicate / J1 origin
The active USB-C programming connector is J9. Schematic inspection shows no active J1 USB-C connector instance remaining. Some net portal labels still contain historical text such as
U1 IO20 - J1 D+ and U1 IO19 - J1 D-; these are label names only, not a second connector. They connect to the actual USB data nets that terminate on J9.The duplicate likely came from an earlier USB-C connector placement before the final J9 connector was added; the actual duplicate component has been removed/merged out of the schematic.
Duplicate reference scan
The dedicated duplicate-reference ERC check reports no open duplicate-reference errors or warnings.
Current summary scan shows only intentional repeated utility objects:
- Net portals: multiple labels by design.
- Ground symbols: multiple symbols tied to the single GND net by design.
- No Connect symbols: multiple by design.
Real functional component references are unique in the inspected summary. No second J1 connector is present.
Power tree integrity
Pass at schematic level.
- +14V_BUS is defined as fused system bus after the battery ideal-diode mux and F1.
- +3V3 is generated from +14V_BUS by U3 TPS563200DDCR.
- ESP32-S3, MAX31855, MAX3485, INA226 monitors, and logic pull-ups are powered from +3V3.
- Review checks for decoupling capacitors and capacitor voltage rating returned no open errors/warnings in the latest query.
Key local decoupling present:
- U1 ESP32-S3: 10 µF + 0.1 µF on +3V3.
- U3 TPS563200: VIN 10 µF + 0.1 µF, output 22 µF + 0.1 µF, bootstrap 0.1 µF.
- U4 MAX31855: 10 µF + 0.1 µF on +3V3.
- U5 MAX3485: 0.1 µF on +3V3.
- U6A INA226: 10 µF + 0.1 µF on VS.
- U6B INA226: 10 µF + 0.1 µF on VS.
- LM74700-Q1 controllers: 1 µF VCAP/VS bypass capacitors present.
Ground integrity
Pass at schematic level.
- Single common GND net is used for power, MCU, logic, thermocouple amplifier, DMX transceiver, shunts, USB ground, and connectors.
- DMX shield uses a separate DMX_SHIELD net coupled to PCB GND through the intended shield-isolation network.
- No isolated ground nets were found other than the intentional DMX shield isolation structure.
MCU GPIO assignment review
Pass at schematic level.
GPIO assignments observed:
- IO0: ESP32_BOOT_IO0 / BOOT switch
- IO4: HEATER_PWM and heater-active indicator LED drive
- IO5: PUMP_PWM
- IO6: FAN_PWM reserved label only
- IO7: STATUS_LED_1 / UI header LED output
- IO8: STATUS_LED_2 / UI header LED output
- IO9: ENCODER_A
- IO10: ENCODER_B
- IO11: ENCODER_BTN
- IO12: SPI_MOSI reserved label only; MAX31855 does not use MOSI
- IO13: SPI_MISO from MAX31855 SO
- IO14: SPI_SCK to MAX31855 SCK
- IO15: SPI_CS_MAX31855
- IO16: I2C_SDA
- IO17: I2C_SCL
- IO18: DMX_UART_RX from MAX3485 RO
- IO19: USB_D_N
- IO20: USB_D_P
- IO21: DMX_UART_TX to MAX3485 DI
- IO35: DMX_DIR to MAX3485 DE and /RE
- IO36: HEATER_CURRENT_SENSE reserved/optional
- IO37: FAULT_LED
No GPIO was found assigned to two unrelated active functions. IO4 intentionally drives both the heater MOSFET gate path and the heater-active LED indicator; that is acceptable because the LED indicates the same PWM signal.
Current paths and layout requirements
Schematic pass; layout constraints still required.
- Heater path is a high-current path and must be implemented with wide copper pours/traces sized for at least 15 A continuous.
- Battery input mux and +14V_BUS path must be implemented with copper sized for the 25 A fuse/current rating.
- Pump path should be sized for at least 1 A despite expected load being about 250 mA.
- Heater return shunt is 5 mΩ and should use Kelvin-style sense routing to the INA226 / sense ADC area where applicable.
Thermal considerations
Schematic pass; layout-dependent.
- Q1 heater MOSFET must be placed in the high-current/thermal area with large copper area and thermal vias/pours as appropriate.
- U3 buck converter must have a compact power loop and enough copper on VIN, SW, GND, and +3V3 output for heat spreading.
- Keep the heater/power switching area physically separated from thermocouple/MAX31855 analog sensing.
ERC status
Latest Electrical Rule Checks query: no open ERROR/WARNING/OPEN items.
DRC status
Current DRC is not clean because the PCB has not been laid out/routed yet.
Open DRC categories observed:
- Airwires: expected before routing; numerous unrouted nets remain.
- Overlapping copper: present in the current unorganized/default placement state and must be resolved during placement/layout.
The current layout summary shows a 4-layer board already configured, but board outline is currently 160 mm x 100 mm and components are not yet arranged for the target 80 mm x 60 mm outline. The layout tool also reported routing congestion around the MCU, thermocouple, buck, and heater areas, so components should be deliberately placed before routing.
Layout gate recommendation
Do not route yet. Proceed next to PCB layout setup and placement:
- Set target board outline to approximately 80 mm x 60 mm.
- Add M3 mounting holes at the corners.
- Keep heater/high-current power section thermally and electrically separated from MAX31855 thermocouple sensing.
- Keep U3 buck regulator power loop compact but away from thermocouple inputs.
- Put DMX XLR connectors and USB-C connector on board edges.
- Place ESP32-S3 with antenna/keepout respected.
- Use a solid GND reference plane and avoid splitting the ground plane under signal return paths.
Final schematic readiness
The schematic is ready to proceed to intentional PCB layout placement, with the caveat that DRC cannot be clean until placement/routing is performed.
Scope
User follow-up confirmations
U6B decoupling
Ideal-diode mux MOSFET designators
USB-C duplicate / J1 origin
Duplicate reference scan
Power tree integrity
Ground integrity
MCU GPIO assignment review
Current paths and layout requirements
Thermal considerations
ERC status
DRC status
Layout gate recommendation
Final schematic readiness
