PCB Design for Fog Generator

Worked

flux

Stopped by execution credits before I could finish the full schematic update or run ERC.

Completed so far:

Removed obsolete 14 V parallel ideal-diode mux parts: U10/U11, Q10/Q11, C1/C2, R1–R4.
Removed old TPS563200 17 V buck section: U3, L1, C5–C9, R5–R7.
Removed old pump MOSFET driver and 2-pin pump connector: Q2, R16, R17, D2, J4.
Renamed global power nets:
- +14V_BUS → +28V_BUS
- +14V_MUX → +28V_OR_PRE_FUSE
- VBAT_A_IN → VBAT_SERIES_IN
- PUMP_PWM → STEPPER_STEP
Added main new 28 V architecture parts:
- U_BB LM5175PWPT buck-boost controller
- U3 TPS54561DPRT wide-VIN 3.3 V buck regulator
- J12 logical 6-pin LEMO input connector
- J4 5-pin JST-XH stepper pump connector
- U_DIODE_1/U_DIODE_2 LM74700-Q1 ideal-diode OR controllers
- Q_DIODE_1/Q_DIODE_2/Q_BB1–Q_BB4 using TSM170N06CP_ROG 60 V / 38 A MOSFETs as library substitutes because FDP18N40 was not found
- L_BB 47 µH / 15 A generic inductor placeholder
Added and partially wired:
- LEMO input filter caps
- LM5175 bootstrap, soft-start, compensation, RT, UVLO, and feedback passives
- LM74700 1 µF VCAP bypass caps and gate networks
- TPS54561 input/output caps, bootstrap cap, feedback divider, EN/UVLO, SS, RT, and compensation placeholders
- Stepper connector pins for +28V_BUS, GND, STEPPER_STEP, STEPPER_DIR, STEPPER_ENABLE
Updated existing metadata:
- C3 to 4700 µF / 50 V bulk
- C4 to 50 V HF bypass
- F1 marked 25 A / 50 V minimum requirement
- J3 heater label/role updated for 28 V 200 W
- Q1 metadata updated to the 60 V MOSFET substitute

Important unresolved items:

ERC has not been run after these edits.
LM5175 datasheet correction: LM5175 VIN max is 42 V, not 60 V. It may still work for a 28 V system, but it is not a 60 V input controller.
The exact LEMO EGG.1B.306 library footprint was not found; J12 is currently a logical 6-pin connector placeholder.
The LM5175 current-sense implementation is only placeholder-wired; the proper high-power current-sense resistor/network still needs detailed design.
INA226 monitor wiring is not fully resolved after the architecture change; U6B/R21 are still in an intermediate/orphaned state and need reconnection to the intended +28 V measurement point.
PCB layout is now invalid for this revised architecture and will need a fresh placement/routing pass after the schematic is cleaned.

Clean unresolved issues

Run ERC/DRC

Find 60V controller

Find LEMO footprint

Design current sense

Files

Schematic

Layout

Preview

DRC Cleanup Status — Remaining Airwires and Copper Issues

Date: 2026-05-27

Summary

A focused cleanup pass was performed without running another generic autoroute. Live review was re-run after cleanup.

Fixed in this pass

Removed the reported dangling trace warning (Trace 5d7b).
Removed the two reported floating smart-via / through-hole copper islands (0a0f3d77, bbb9c3cb).
Re-ran DRC after the cleanup.

Remaining live DRC status after cleanup

Airwires: 25 errors remain.
Floating copper: 0 errors.
Dangling traces: 0 warnings.
Multiple fills: 1 error remains.
Total live DRC errors in the requested categories: 26.

Remaining airwires from live review

The review engine reports several airwires by pad UID rather than resolved human net names. Where the UID could be mapped through the schematic/layout data, the likely net and endpoints are listed below.

Table

Priority	Reported item	Mapped net / class	Endpoints from live review	Status / obstruction
Signal	D+	USB_DP_JACK_SERVICE	J9 D+ duplicate/service pad to J9 D+ duplicate/service pad and SJ2 P1 path	Still unrouted. Needs short manual USB route through SJ2; current router treats USB-C duplicated pins as blocked.
Signal	P1	USB_DP_JACK_SERVICE	SJ2 P1 to J9 D+ service pad	Still unrouted. SJ2 must remain inline with D+; manual route required.
Signal	IO19	USB_D_N	U1 IO19 to J9 D−	Still unrouted. USB-C duplicated D− pads are blocked for autorouter.
Signal	D−	USB_D_N	J9 D− duplicate pads	Still unrouted. Needs short manual D− completion.
Signal	VBUS	USB_C_PROG_VBUS_TP	J9 VBUS duplicate pads	Still unrouted. This is a test-point/duplicate-pad tie; can be manually shorted or intentionally removed if VBUS test access is not required.
High current / sense	VBUS / IN+	VBAT_B_IN	U6B VBUS / IN+ current-sense pins	Still unrouted. These are INA226 high-side sense connections; 4 mm copper cannot enter IC pins, so neckdown/Kelvin traces are required from the battery shunt pads.
High current / sense	P1 / P2 items around C6 and +14V fill	+14V_BUS / GND around buck input C6 and fill `6f09fcfb`	C6 pads, fill, stitching via, and nearby passives	Still unrouted. Needs corrected power-pour geometry plus narrow neckdowns into small pads.
High current	D	HEATER_SW	Q1 drain to snubber/load copper	Still unrouted. Needs heater copper pour/manual high-current copper completion, not a narrow autorouted trace.
Power / logic	A0 / VS / VCC / P1-style items	+3V3/GND around U6B, C12, and related decoupling	Mixed small IC/passive pads	Still unrouted. Most are small-pad connections into +3V3/GND regions after prior fill cleanup.
Unknown trace-endpoint items	Trace 5830, Trace 9b98, Trace ecd3, Trace c59b, Trace f6e3	Partially mapped from trace node to pad UID only	Trace node to component pad	Still unrouted. These appear to be partially completed route stubs or fill-edge connections and need manual trace continuation/removal after full copper review.

Floating copper cleanup

Table

Reported floating item	Action taken	Result
`0a0f3d77` smart-via / through-hole island	Deleted orphaned via/copper island	Cleared
`bbb9c3cb` smart-via / through-hole island	Deleted orphaned via/copper island	Cleared

Multiple-fills issue

Live review still reports one multiple-fills error on Top Bottom with fill UIDs:

1d4a0738-0ffb-4c96-a312-e4914489983c
963730da-10d6-4fe8-93ec-8712d4d716a5
c23d850f-860c-4711-ad7e-513b8b155246
6f09fcfb-9b58-4c99-9821-15be927144a6

Attempted deletion through the cleanup tool was rejected because these are generated/virtual fill nodes, not directly deletable layout nodes. The conflict therefore remains and needs a fill-rule/plane-region edit rather than trace deletion.

Recommended correction:

Recreate high-current fills as explicit non-overlapping zones, one net per physical region per layer.
On layer 3, split +14V_BUS and +3V3 with a clear gap.
On layers 1 and 4, keep high-current pours local to their current paths and do not overlap with other net fills on the same layer.
Re-run fill generation and DRC.

Current blockers

The remaining issues cannot be finished safely with another generic autoroute. They require explicit manual copper/zone editing or a fill-region tool that can split and assign copper pours, plus short manual USB routing through SJ2.

Preservation checks

ESP32 antenna keepout: still present; no protected-keepout intrusion was reported in the latest review.
TC analog separation: placement still supports the required 20 mm separation from heater/buck power areas, but final routed TC trace geometry should be inspected after manual route completion.
Q1/R15 thermal copper: the intent remains, but the multiple-fill conflict means the high-current thermal pours are not yet in a verified manufacturable state.