COM-HPC Carrier Layout
Thought for 15 sec
I’ll update Version 5.0 front-view visuals only so the Compute Module is drawn with correct 90 mm × 100 mm proportions and occupies the appropriate larger area. Version 4.0 stays locked.
Worked for 3 mins 46 sec
Thought for 26 sec
Created image.
You can move the component labels off to the side of the PCB
Worked for 4 mins 54 sec
Redone for Tiny Tim Version 5.0 front view.
Changes applied:
- Compute Module is shown much larger with intended 90 mm × 100 mm proportions.
- Carrier board remains 105 mm × 115 mm.
- Labels moved off the PCB as side callouts to reduce clutter.
- Version 4.0 remains locked and unchanged.
Updated file:
Updated Front View
Image
Redo rear and review
Lock Version 5.0
Compare front views
Check label accuracy
Improve compute module fit
Refine this doc
Ask about this doc
Tiny Tim Version 4.0 Downloadable Text Export Package
Export Package Status
This is the consolidated text export package for Tiny Tim Version 4.0.
Version 4.0 is locked as a documentation / schematic-concept milestone. It is prepared for external review, requirements sharing, sourcing review, and continuation planning.
It is not a manufacturing-ready PCB export.
Lock Rule
No connector, geometry, label, quantity, schematic wiring, visual, placement, or documentation change should be made to Version 4.0 unless the user explicitly requests:
- unlock Version 4.0, or
- create/start Version 4.1.
Export Readiness Classification
Table
| Export Type | Version 4.0 Status |
|---|---|
| Text/document export | Ready |
| Visual concept export | Ready as linked concept images |
| Schematic review export | Partial / conceptual |
| BOM candidate review | Ready as candidate BOM |
| Manufacturing Gerbers | Not ready |
| Pick-and-place | Not ready |
| STEP/3D PCB model | Not ready |
| Fabrication package | Not ready |
Manufacturing export is blocked because:
- The COM-HPC Mini connector Samtec ASP-230336-03 is not yet available as a usable Flux part.
- Several selected connector footprints still require import/create.
- The board is not placed/routed as a real manufacturable PCB.
- ERC/DRC still has expected unresolved warnings/errors from incomplete pin mapping and airwires.
Locked Version 4.0 Master Links
Table
| File | Purpose |
|---|---|
| Tiny Tim Version 4.0 Locked Export Package | Master export index and lock status. |
| Project Specification | Master requirements/specification and current design state. |
| Tiny Tim Version 4.0 | Version 4.0 concept checkpoint. |
| Current State Visuals: Tiny Tim Version 4.0 | Locked Version 4.0 visual references. |
| Tiny Tim Vertical Connectors v2.0 | Active connector table and selected connector candidates. |
| Tiny Tim Version 4.0 Implementation Checklist | Implementation status, next steps, and blockers. |
| Tiny Tim Version 4.0 Part Verification Results | Part-number and footprint verification log. |
| Tiny Tim Version 4.0 BOM Candidates and Connector Verification Review | BOM candidates, Flux-ready parts, missing footprint registry, and connector review. |
| Tiny Tim Version 4.0 Connector Pin Mapping | Provisional lane assumptions and connector-side USB/PCIe net mapping. |
| Tiny Tim Version 4.0 Power Budget | Preliminary power budget and non-PoE 12 V input policy. |
| COM-HPC Mini Connector Search Results | COM-HPC connector search and import blocker details. |
| Tiny Tim Version 4.0 PoE Solution — Discontinued | Historical PoE analysis, marked do-not-implement. |
| Tiny Tim Version 3.0 Size Optimization Estimate | Prior size-reduction rationale for 105 mm x 115 mm. |
Current State Visuals
Source file: Current State Visuals: Tiny Tim Version 4.0
Front View Reference
Image
Rear View Reference
Image
Visual limitation: these are concept images, not CAD-accurate PCB layout screenshots.
Locked Version 4.0 State Summary
Table
| Item | State |
|---|---|
| Board concept target | 105 mm x 115 mm |
| Live physical connector components | 24 |
| Live unique physical BOM parts | 11 |
| Schematic nets | 34 |
| PCB layout status | Concept/default layout state only; not manufacturing-ready |
| Primary power input | AMASS XT60PW-M, J_12VIN1, nets 12V_IN and PGND |
| COM-HPC Mini carrier connector | Samtec ASP-230336-03, 10 mm stack height; blocked pending importable EDA library |
| PoE | Stopped / do not implement |
Live BOM Snapshot
Table
| Qty | Part | MPN | Manufacturer | Designators |
|---|---|---|---|---|
| 5 | JST-GH 4-pin | BM04B-GHS-TBT(LF)(SN) | JST | J_GH4_1..J_GH4_5 |
| 3 | JST-GH 6-pin | BM06B-GHS-TBT(LF)(SN) | JST | J_GH6_1..J_GH6_3 |
| 3 | JST-GH 7-pin | BM07B-GHS-TBT(LF)(SN)(N) | JST | J_GH7_1..J_GH7_3 |
| 1 | PicoBlade fan connector | 53047-0410 | Molex | J_FAN1 |
| 1 | Rear PCIe FFC | 505110-1692 | Molex | J_PCIE_FFC1 |
| 1 | XT30 BAT OUT | XT30PW-M30.G.Y | AMASS | J_BAT_OUT1 |
| 1 | XT60 primary 12 V input | XT60PW-M | AMASS | J_12VIN1 |
| 3 | Vertical USB-C Gen2 | USB-C31-S-VT-CS4-BK-PP-T/R | Adam Tech | J_USBC1..J_USBC3 |
| 1 | M.2 E-key | 2199230-4 | TE Connectivity | J_M2E1 |
| 1 | M.2 M-key | MDT420M01501 | Amphenol | J_M2M1 |
| 4 | FAKRA GMSL candidate | 7-2287906-0 | TE Connectivity | J_GMSL1..J_GMSL4 |
Missing Exact Footprints / Components Still Required
Table
| Required Part | Function | Status |
|---|---|---|
| Samtec ASP-230336-03 | COM-HPC Mini carrier plug | Blocked; needs importable EDA library package or Flux library creation. |
| Bel / TRP G55-122N-155 | 10GbE RJ45 MagJack | Needs import/create. |
| Molex 5031590600 | CLIK-Mate board-side receptacle | Needs import/create if retained. |
| Molex 0525592253 / 52559-2253 | CSI vertical FFC | Needs import/create. |
| TE 2438987-1 | USB-A vertical | Needs import/create. |
| Molex 0476591100 / 47659-1100 | HDMI vertical | Needs import/create or approve close Flux alternative. |
| Molex 2047110001 | TBT/USB4 Type-C connector candidate | Needs import/create and architecture definition. |
| XT60PW-M30.G.Y.T | BAT IN/reference footprint | Needs import/create if separate from J_12VIN1 policy. |
Connector-Side Pin Mapping Summary
See full details in Tiny Tim Version 4.0 Connector Pin Mapping.
Mapped so far:
J_12VIN1:Posto12V_INJ_12VIN1:NegtoPGND- USB-C VBUS/GND/USB2/SuperSpeed first-orientation nets for
J_USBC1..J_USBC3 - Rear PCIe FFC
J_PCIE_FFC1using Raspberry Pi-style 16-pin PCIe FFC pinout - Controlled-impedance metadata:
- USB2: 90 Ω differential
- USB3 / PCIe: 85 Ω differential
Not mapped yet:
- COM-HPC Mini pins
- M.2 physical pins
- USB-C CC/SBU and second-orientation SuperSpeed pins
- TBT/USB4 full architecture
- GMSL coax mapping
- JST-GH auxiliary headers
- fan pin order
- battery path beyond connector candidates
Power Summary
See full details in Tiny Tim Version 4.0 Power Budget.
Key decisions:
- PoE stopped / do not implement.
- Primary non-PoE power input is 12 V via AMASS XT60PW-M.
- Nominal design target: 12 V / 12 A minimum.
- Peak/unrestricted target: 25 A class.
- Estimated full-system nominal load: about 108 W.
- Estimated peak/turbo unrestricted load: about 225 W.
COM-HPC Connector Blocker
Selected connector:
- Samtec ASP-230336-03
- COM-HPC 400-position male carrier plug
- 10 mm stack height
- column termination
Current blocker:
- Not found as a usable Flux library part.
- Public Samtec PDF/PADS resources exist.
- Current import path requires an actual EDA library package: KiCad
.kicad_sym + .kicad_mod, Altium.SchLib + .PcbLib, Eagle.lbr, EasyEDA JSON, or ZIP. - Fake placeholder pins were intentionally not created.
Final Checks at Lock
Table
| Check Area | Result |
|---|---|
| Live BOM | 11 unique physical parts / 24 instances |
| Schematic nets | 34 |
| Layout summary | 160 mm x 100 mm default/auto layout state, 4 copper layers; not the locked 105 mm x 115 mm manufacturing target |
| ERC | Expected floating-pin warnings remain; COM-HPC source connector and remaining subsystem mappings incomplete |
| DRC | Airwires present; layout is not ready for manufacturing export |
| Manufacturing export | Blocked until real board outline, placement, missing footprints, routing, and DRC closure are complete |
Recommended Version 4.1 Start Point
Version 4.1 should begin with:
- Import/create Samtec ASP-230336-03.
- Import/create missing exact connector footprints.
- Replace conceptual/default layout with 105 mm x 115 mm board setup.
- Add COM-HPC Mini connector and map provisional nets to real pins.
- Continue pin mapping subsystem by subsystem.
- Place components and route high-speed interfaces with controlled impedance.
How to Use This Text Export
This document is suitable for:
- copying into an external text file,
- printing to PDF from the browser,
- sharing for requirements/design review,
- sourcing and connector follow-up,
- planning Version 4.1.
It is not a substitute for a fabrication package.
Export Package Status
Lock Rule
Export Readiness Classification
Locked Version 4.0 Master Links
Current State Visuals
Front View Reference
Rear View Reference
Locked Version 4.0 State Summary
Live BOM Snapshot
Missing Exact Footprints / Components Still Required
Connector-Side Pin Mapping Summary
Power Summary
COM-HPC Connector Blocker
Final Checks at Lock
Recommended Version 4.1 Start Point
How to Use This Text Export
