COM-HPC Carrier Layout
Thought for 15 sec
I’ll update Version 5.0 front-view visuals only so the Compute Module is drawn with correct 90 mm × 100 mm proportions and occupies the appropriate larger area. Version 4.0 stays locked.
Worked for 3 mins 46 sec
Thought for 26 sec
Created image.
You can move the component labels off to the side of the PCB
Worked for 4 mins 54 sec
Redone for Tiny Tim Version 5.0 front view.
Changes applied:
- Compute Module is shown much larger with intended 90 mm × 100 mm proportions.
- Carrier board remains 105 mm × 115 mm.
- Labels moved off the PCB as side callouts to reduce clutter.
- Version 4.0 remains locked and unchanged.
Updated file:
Updated Front View
Image
Redo rear and review
Lock Version 5.0
Compare front views
Check label accuracy
Improve compute module fit
Refine this doc
Ask about this doc
Tiny Tim Version 4.0 Implementation Checklist
Lock Notice
Tiny Tim Version 4.0 is locked. Do not change connector selections, schematic wiring, visual references, placement, geometry, or documentation unless the user explicitly unlocks Version 4.0 or starts Version 4.1.
Locked export index: Tiny Tim Version 4.0 Locked Export Package
Goal
Move Tiny Tim Version 4.0 from concept images to a real executable Flux design: verified parts, schematic blocks, footprints, board outline, placement, routing constraints, DRC/ERC, and exportable design files.
Baseline
- Working version: Tiny Tim Version 4.0
- Concept outline: 105 mm x 115 mm
- Connector basis: Tiny Tim Redo with Vertical Connectors v2.0.pptx
- Connector geometry rule: vertical receptacle / top-entry unless explicitly changed
- Current project state: first schematic connector block created; PCB layout/placement/routing not started yet
- Current schematic state: first Flux-ready connector block plus primary XT60 12 V input added; live BOM has 11 unique physical parts / 24 instances. USB-C and rear PCIe FFC connector-side nets are now labeled; schematic has 34 nets. Layout is not created yet.
- Latest verification file: Tiny Tim Version 4.0 Part Verification Results
- Latest BOM/connector review file: Tiny Tim Version 4.0 BOM Candidates and Connector Verification Review
Phase 1 — Part Number and Footprint Verification
Table
| Item | Task | Status | Decision / Next Action |
|---|---|---|---|
| COM-HPC Mini type connector | Identify exact carrier connector, pinout, keepout, mating height, footprint | Approved connector selected | Use Samtec ASP-230336-03, COM-HPC 400-position male carrier plug, 10 mm stack height, column termination, selected for more clearance and cooling. Exact Flux library part not found; missing-part request submitted; footprint import/create likely required. |
| COM-HPC connector import/create | Import/create selected COM-HPC connector | Blocked | Exact Samtec ASP-230336-03 is still not in Flux library. Current import tool needs usable EDA library files such as KiCad .kicad_sym + .kicad_mod, Altium .SchLib + .PcbLib, Eagle .lbr, EasyEDA JSON, or ZIP. Public PDF/PADS references are not enough for automated import in this session. |
| JST-GH BM04B-GHS-TBT | Verify board-mount top-entry footprint and mating GHR-04V-S | Confirmed usable | Flux library part found: bf459cba-67ba-4bb7-b0bb-3a6f512744c7. |
| JST-GH BM06B-GHS-TBT | Verify board-mount top-entry footprint and mating GHR-06V-S | Confirmed usable | Flux library part found: 4d0ff384-7425-4ee8-8786-5dafb8888048. |
| JST-GH BM07B-GHS-TBT | Verify board-mount top-entry footprint and mating GHR-07V-S | Confirmed usable | Flux library part found: c9192a01-1eb5-4afe-af39-3a12fb37cf9c. |
| Molex CLIK-Mate power input | Verify/select board-side connector | Reasonable replacement selected | Use Molex 5031590600, 6-circuit vertical through-hole CLIK-Mate board receptacle. It mates with 5025780600 plug housing. Note: final input voltage/current policy may replace this connector due to 12 V high-current budget. |
| Molex PicoBlade 53047-0410 | Verify board-mount footprint and cable mate | Confirmed usable pending orientation check | Flux library part found: 40a04ad5-2abb-475e-94c4-4f279f16f1ff. |
| 22-pin CSI FFC | Select exact vertical/top-entry 0.5 mm FFC part and footprint | Reasonable selection made | Use Molex 0525592253 / 52559-2253, vertical 22-position 0.5 mm slider ZIF FFC/FPC connector. Not in Flux library; missing-part request previously submitted. |
| Molex 505110-1692 | Verify PCIe/USB FFC use, mechanical footprint, and orientation | Confirmed for 1x rear FFC; geometry accepted as right-angle | Use 1x Molex 505110-1692 for rear PCIe/USB FFC. Flux library part 0ce204fd-1b64-4637-bcd2-a99f708b27f4; 16-pin right-angle bottom-contact FFC. |
| XT60 primary 12 V input | Select high-current primary 12 V connector | Finalized and added | Use AMASS XT60PW-M as J_12VIN1. Nets created: 12V_IN and PGND. Policy target: 12 V / 12 A nominal minimum, 25 A-class peak. XT60PW-M30.G.Y.T remains BAT IN/reference footprint candidate. |
| XT30PW-M30 | Verify Amass PCB-mount footprint, current rating, and vertical orientation | Confirmed usable pending orientation check | Flux library part found: d7014d62-22f9-4be9-9625-3dc4b41c4bdd. |
| Vertical RJ45 10GbE | Select exact 10G-capable RJ45/magnetics part | Recommended replacement selected; PoE stopped | Replace incorrect TE 5555165-1 with Bel / TRP G55-122N-155 for 10GBASE-T data. Do not implement PoE unless the user explicitly reopens PoE design. |
| Vertical USB-A | Select exact vertical USB-A receptacle footprint | Reasonable selection made | Use TE Connectivity 2438987-1, vertical USB Type-A USB 3.1/3.2 Gen 2 9-position through-hole receptacle. Not in Flux library; missing-part request submitted. |
| Vertical USB-C OTG | Select exact vertical USB-C receptacle footprint and role wiring | Reasonable selection made | Use Adam Tech USB-C31-S-VT-CS4-BK-PP-T/R for 3x USB-C OTG/data ports; Flux library part b3a7bff8-9e2a-4b80-b8cc-bc7709bf97ce. |
| Vertical HDMI Type A | Select exact vertical HDMI Type A footprint | Reasonable selection made | Use Molex 0476591100 / 47659-1100, vertical HDMI Type A 19-circuit receptacle. Not in Flux library; missing-part request submitted. |
| M.2 E/B-key 2230 | Use approved real M.2 connector instead of Molex 105450-0401 | Approved replacement selected | Use TE Connectivity 2199230-4. Flux library part: 757ea7be-ffcd-4c93-b746-0459da7c39c0. Add 2230 standoff/mechanical retention. |
| M.2 M/B-key 2280 | Use approved real M.2 connector instead of Molex 105450-0101 | Approved replacement selected | Use Amphenol MDT420M01501. Flux library part: 220aa0e1-7cd7-4889-a366-b5659a32717a. Add 2280 standoff/mechanical retention. |
| Fakra GMSL | Select exact vertical Fakra / multi-Fakra parts and footprints | Reasonable selection made with geometry caveat | Use TE Connectivity 7-2287906-0 as 4x GMSL coax FAKRA candidate; Flux library part 59283499-dd1b-4f81-8a33-08268027fd51. It is right-angle/edge-mount, not top-entry, because no verified vertical FAKRA was found. |
| Type-C TBT / USB4 | Replace invalid Molex 105450-0201 with real vertical USB4-capable Type-C connector candidate | Reasonable connector candidate selected; architecture still open | Use Molex 2047110001 as vertical USB-C USB4 40 Gbps connector candidate. Not in Flux library; missing-part request submitted. TBT still requires controller/retimer, lane mapping, compliance, and routing architecture. |
Phase 2 — Mechanical Definition
- Confirm COM-HPC Mini type connector datum, mating direction, keepouts, mounting holes, and module overhang.
- Confirm 105 mm x 115 mm board outline can physically support rear M.2 2280 and front vertical connector set.
- Define front-side and rear-side keepout/cable-access zones.
- Define mounting holes.
- Confirm maximum component heights on both sides.
Phase 3 — Electrical Architecture
- Define COM-HPC Mini type pin mapping to all external connectors.
- Define power architecture around
J_12VIN1primary 12 V input, BAT IN, BAT OUT, protection, ideal diode/power path if needed, regulators, current sensing if needed. - PoE design is stopped. Use the Version 4.0 preliminary power budget for non-PoE primary power planning: nominal full system ~108 W, peak/turbo unrestricted ~225 W. Recommended primary input is 12 V, 12 A minimum nominal or 25 A class for unrestricted peak/turbo.
- Define 10GbE PHY/magnetics assumptions or confirm COM-HPC module provides required interfaces.
- Define USB/TBT/HDMI/CSI/GMSL/PCIe signal ownership and lane mapping.
- Define low-speed JST-GH pinouts.
Phase 4 — Stackup and Design Rules
Preliminary recommendation: 8-layer PCB until proven otherwise, because Tiny Tim includes PCIe x4, USB 3.x/TBT, HDMI, 10GbE, CSI, GMSL, dense connectors, and rear M.2 routing.
Initial controlled-impedance targets:
Table
| Interface | Target |
|---|---|
| PCIe | 85 ohm differential |
| USB 3.x / USB-C high-speed | 85 ohm differential |
| USB 2.0 | 90 ohm differential |
| HDMI | 100 ohm differential |
| Ethernet MDI | 100 ohm differential |
| CSI / MIPI | Usually 100 ohm differential; confirm module/vendor requirements |
| GMSL coax/Fakra | 50 ohm single-ended/coax transition; confirm device requirements |
Phase 5 — Schematic Capture
Recommended block order:
- Power input and battery connectors.
- COM-HPC Mini type connector block.
- Low-speed JST-GH headers.
- USB-A / USB-C / TBT connectors.
- HDMI.
- CSI FFC.
- GMSL Fakra.
- RJ45 / 10GbE.
- Rear M.2 and PCIe/USB FFC.
- Protection, ESD, fuses, common-mode chokes, and test points.
Phase 6 — Layout
- Set board outline to 105 mm x 115 mm.
- Place COM-HPC Mini type connector and keepout first.
- Place rear M.2 2280, rear M.2 2230, and rear PCIe/USB FFC.
- Place front vertical connectors using Version 4.0 visual intent.
- Run placement DRC/mechanical clearance checks.
- Configure stackup and impedance rules.
- Route high-speed groups first, then power, then low-speed.
- Run DRC/ERC and iterate.
Phase 7 — Outputs
When schematic/layout are real and validated, generate:
- Gerber / ODB++ / IPC-2581 manufacturing files.
- BOM.
- Pick-and-place.
- STEP/3D model.
- Assembly drawings.
- Bring-up and validation plan.
Immediate Next Actions
- Obtain/upload an importable EDA library package for Samtec ASP-230336-03 or wait for Flux library creation. Do not wire fake COM-HPC pins.
- Finish non-PoE power policy details: battery path, protection, ideal diode/power mux, regulator tree, and external port power caps. Primary 12 V connector is selected as
J_12VIN1 = AMASS XT60PW-M. - Import/create missing connector footprints: Samtec ASP-230336-03, Bel G55-122N-155, Molex 5031590600, Molex 0525592253, TE 2438987-1, Molex 0476591100, Molex 2047110001, XT60PW-M30.G.Y.T.
- Define TBT/USB4 architecture beyond the connector: controller/retimer need, lane mapping, compliance, and routing rules.
- Continue schematic capture by adding missing/imported connector parts and then define connector pin mapping. The first Flux-ready connector block is already in the schematic.
Connector Import/Create Note
Usable automatic import requires EDA library files, not just datasheet URLs. If exact missing connector footprints are not already in Flux, upload KiCad
.kicad_sym + .kicad_mod, Altium .SchLib + .PcbLib, Eagle .lbr, EasyEDA JSON, or a ZIP containing those files. Datasheets alone are recorded as evidence but do not produce complete schematic symbols and PCB footprints in this session.Pin Mapping Status
Initial connector pin mapping is captured in Tiny Tim Version 4.0 Connector Pin Mapping.
J_12VIN1, USB-C connector-side nets, and rear PCIe FFC connector-side nets are mapped with controlled-impedance metadata. M.2 lane allocation is documented provisionally but not physically wired yet; final COM-HPC Mini mapping remains blocked on exact lane/pinout data. Current expected ERC state: 271 floating-pin warnings.Lock Notice
Goal
Baseline
Phase 1 — Part Number and Footprint Verification
Phase 2 — Mechanical Definition
Phase 3 — Electrical Architecture
Phase 4 — Stackup and Design Rules
Phase 5 — Schematic Capture
Phase 6 — Layout
Phase 7 — Outputs
Immediate Next Actions
Connector Import/Create Note
Pin Mapping Status
